Simulation-based RISC-V DSP accelerator verification and FPGA-based data transmission on ZCU104 platform

Abstract

This thesis focuses on the verification of a RISC-V DSP accelerator with A-Core processor, emphasizing functional verification through simulation, and the verification of FPGA-based data transfer on the ZCU104 platform. The primary goal is to ensure signal processing accuracy and system functionality, providing a detailed account of the verification processes while addressing practical challenges. The reliability of the RISC-V DSP accelerator with A-Core processor for future use in contemporary communication systems is confirmed by this work through the analysis of important performance indicators and the documentation of debugging methods.

The functional verification of the DSP accelerator was conducted in a simulation environment, with metrics such as Error Vector Magnitude (EVM), Power Spectral Density (PSD), and Adjacent Channel Leakage Ratio (ACLR) evaluated to assess signal fidelity and performance. These analyses highlighted the effects of specific design elements, including the inclusion of the Up Rate Converter (URC), on overall system behavior. This work provides valuable insights into the DSP accelerator's functionality and forms a foundation for its potential integration into hardware platforms.

In addition, this thesis verifies data transfer within the FPGA-based platform, leveraging the A-Core processor and the ZCU104 board. With the FPGA implementation developed by the Electronic Circuit Design (ECD) group, this work documents the challenges encountered during the verification process, including open-source setup issues, configuration mismatches, and debugging errors. Practical solutions to these challenges are detailed, offering a reference for future researchers working on similar projects.

The results of this thesis demonstrate the effectiveness of the verification methodologies employed, ensuring the functional correctness of the DSP accelerator and validating FPGA-based data transfer. This thesis provides a solid foundation and direction for further research on FPGA verification of the DSP accelerator. The systematic approach, insights, and practical methods documented here contribute to advancing RISC-V-based DSP accelerator design, ensuring performance reliability and scalability in communication systems.