Hardware Design of Decoder for Low-Density Parity Check Codes

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Volume Title

Elektroniikan, tietoliikenteen ja automaation tiedekunta | Master's thesis
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Authors

Date

2009

Department

Major/Subject

Tietoliikennetekniikka

Mcode

S-72

Degree programme

Elektroniikan ja sähkötekniikan tutkinto-ohjelma

Language

en

Pages

x + 62

Series

Abstract

A hardware decoder architecture is presented in this thesis for quasi-cyclic (QC) low-density parity check (LDPC) codes. The decoder is real-time configurable and supports 15 codes which are combination of 3 rates and 5 lengths. The partly parallel architecture implements layered decoding. A check node decoder is serial and implements min-sum correction algorithm. The proposed design techniques include out-of-order memory-write, two-stage multi-size shifter, serial decoding termination. The decoder consumes about half amount of logic resource on the Xilinx FPGA chip XC2VP50-5F1152. The worst case throughput at 20 iterations ranges from 5 Mbits to 60 Mbits (information bits) per second. Higher throughput can be obtained by the proposed optimisation. Reuse for similar codes is possible.

Description

Supervisor

Östergård, Patric

Thesis advisor

Rautio, Mika

Keywords

low-density parity check (LDPC) decoder, FPGA, multi-rate, multi-length, layered decoding, out-of-order memory-write, multi-size shifter

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https://urn.fi/URN:NBN:fi:aalto-201203071302

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[dipl] Sähkötekniikan korkeakoulu / ELEC