System-Level Design of All-Digital LTE / LTE-A Transmitter Hardware

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master_roverato_enrico_2012.pdf (2.11 MB)

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School of Electrical Engineering | Master's thesis
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Date

2012

Department

Mikro- ja nanotekniikan laitos
Department of Micro and Nanosciences

Major/Subject

Electronic Circuit Design

Mcode

S-87

Degree programme

Language

en

Pages

10+94

Series

Abstract

This thesis presents a detailed system-level analysis of an all-digital transmitter hardware based on the Direct-Digital RF-Modulator (DDRM). The purpose of the presented analysis is to evaluate whether this particular transmitter architecture is suitable to be used in LTE / LTE-A mobile phones. The DDRM architecture is based on the Radio Frequency Digital-to-Analog Converter (RF-DAC), whose system-level characteristics are investigated in this work through mathematical analysis and MATLAB simulations. In particular, a new analytical model for the timing error in the distributed upconversion is developed and verified. Moreover, this thesis reviews the LTE and LTE-A standards, and describes how a baseband environment for signal generation/demodulation can be implemented in MATLAB. The presented system enables much more flexibility with respect to current commercial softwares like Agilent Signal Studio. Simulation results show that the most challenging specification to meet is the out-of-band noise floor, because of the stringent linearity and timing requirements posed on the RF-DAC. This suggests that new means of reducing the out-of-band noise in all-digital transmitters should be researched, in order not to make their design more complicated than for their analog counterpart.

Description

Supervisor

Ryynänen, Jussi

Thesis advisor

Kosunen, Marko

Keywords

CMOS, Direct-Digital RF-Modulator (DDRM), Radio Frequency Digital-to-Analog Converter (RF-DAC), LTE, LTE-A, timing error, noise floor

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https://urn.fi/URN:NBN:fi:aalto-201801081015

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[dipl] Sähkötekniikan korkeakoulu / ELEC