Parallel Hierarchical DC Analysis

Helsinki University of Technology | Licentiate thesis

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Authors

Date

Department

Sähkö- ja tietoliikennetekniikan osasto

Major/Subject

Teoreettinen sähkötekniikka

Mcode

S-55

Language

en

Pages

58

Supervisor

Valtonen, Martti

Thesis advisor

Roos, Janne

Keywords

parallel processing, circuit simulation, Newton-Raphson, multilevel Newton-Raphson

Permanent link to this item

https://urn.fi/URN:NBN:fi:aalto-202104145484

Collections

[lic] Teknillinen korkeakoulu / TKK

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