VHDL Test Bench Approach to ASIC Design Validation and Verification
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Helsinki University of Technology |
Diplomityö
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Instructions for the author
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Date
1996
Department
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Laitteistotekniikka
Mcode
S-88
Degree programme
Language
en
Pages
65
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Description
Supervisor
Skyttä, JormaThesis advisor
Pulkkinen, OttoKeywords
ASIC, ASIC, design flow, SDH, SDH, simulointi, simulation, suunnitteluvuo, test bench, testipenkki, validation, validointi, verification, varmentaminen, VHDL, verifiointi, VHDL