VHDL Test Bench Approach to ASIC Design Validation and Verification

Helsinki University of Technology | Master's thesis

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P1 Ark T80

Authors

Zetterman, Tommi

Date

Department

Tietotekniikan osasto

Major/Subject

Laitteistotekniikka

Mcode

S-88

Language

en

Pages

65

Supervisor

Skyttä, Jorma

Thesis advisor

Pulkkinen, Otto

Keywords

ASIC, ASIC, design flow, SDH, SDH, simulointi, simulation, suunnitteluvuo, test bench, testipenkki, validation, validointi, verification, varmentaminen, VHDL, verifiointi, VHDL

Permanent link to this item

https://urn.fi/URN:NBN:fi:aalto-2020120342849

Collections

[dipl] Teknillinen korkeakoulu / TKK

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