Reconfigurable Signal Processing and DSP Hardware Generator for 5G and Beyond Transmitters

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Journal Title
Journal ISSN
Volume Title
A1 Alkuperäisartikkeli tieteellisessä aikakauslehdessä
Date
2024-01-01
Major/Subject
Mcode
Degree programme
Language
en
Pages
12
Series
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume PP, issue 99
Abstract
The digital front-end of the communication transceivers envisioned for fifth-generation (5G) and beyond requires highly configurable high-performance digital signal processing (DSP) hardware operating at very high sampling rates to accommodate increasing signal bandwidths and support a range of modulation schemes and transmitter architectures. In this article, we present an efficient implementation of a highly configurable DSP hardware generator that can generate high-performance DSP hardware for multiple transmitter architectures including Cartesian, polar, outphasing, and multilevel outphasing modulators. The generated hardware unit, which consists of multistage multirate filters and other required DSP operations, runs at sample rates up to 4 GHz. The hardware supports an adjacent channel leakage ratio (ACLR) down to -48 dB and an error vector magnitude (EVM) of 0.78% with a 7-bit phase signal at a sampling rate of 4 GHz for multilevel outphasing modulation. Digital synthesis of the circuit in a 5-nm complimentary metal-oxide semiconductor (CMOS) process yields a core area consumption of 0.01 mm2 and an estimated power consumption of 37.2 mW for a 200-MHz bandwidth 5G new radio (NR) baseband (BB) signal.
Description
| openaire: EC/H2020/860921/EU//SMArT
Keywords
Hardware, Radio transmitters, Generators, 5G mobile communication, Signal processing, Modulation, Phase modulation
Other note
Citation
Ghosh , A , Spelman , A , Cheung , T H , Boopathy , D , Stadius , K , Gomony , M D , Valkama , M , Ryynänen , J , Kosunen , M & Unnikrishnan , V 2024 , ' Reconfigurable Signal Processing and DSP Hardware Generator for 5G and Beyond Transmitters ' , IEEE Transactions on Very Large Scale Integration (VLSI) Systems , vol. 32 , no. 1 , 10313121 , pp. 4-15 . https://doi.org/10.1109/TVLSI.2023.3326159