All-digital phase-locked loop in 40 nm CMOS for 5.8 Gbps serial link transmitter

dc.contributorAalto-yliopistofi
dc.contributorAalto Universityen
dc.contributor.authorAntonov, Yuryen_US
dc.contributor.authorTikka, Teroen_US
dc.contributor.authorStadius, Karien_US
dc.contributor.authorRyynänen, Jussien_US
dc.contributor.departmentDepartment of Micro and Nanosciencesen_US
dc.date.accessioned2022-03-16T12:51:49Z
dc.date.available2022-03-16T12:51:49Z
dc.date.issued2015-10-16en_US
dc.description.abstractThis paper describes an all-digital phase-locked loop based clock generator for a MIPI M-PHY serial link transmitter. The paper focuses on ADPLL phase accumulator speed optimization, PVT calibration, loop type changing criteria and power saving in phase digitization process. The experimental circuit is implemented in 40 nm CMOS and generates the MIPI M-PHY defined frequencies from 1.2 GHz to 5.8 GHz.en
dc.description.versionPeer revieweden
dc.format.mimetypeapplication/pdfen_US
dc.identifier.citationAntonov , Y , Tikka , T , Stadius , K & Ryynänen , J 2015 , All-digital phase-locked loop in 40 nm CMOS for 5.8 Gbps serial link transmitter . in 2015 European Conference on Circuit Theory and Design, ECCTD 2015 . , 7300035 , IEEE , European Conference on Circuit Theory and Design , Trondheim , Norway , 24/08/2015 . https://doi.org/10.1109/ECCTD.2015.7300035en
dc.identifier.doi10.1109/ECCTD.2015.7300035en_US
dc.identifier.isbn978-1-4799-9877-7
dc.identifier.isbn978-1-4799-9876-0
dc.identifier.otherPURE UUID: 277a0097-e13b-4bc3-bc2d-4ec67be00f40en_US
dc.identifier.otherPURE ITEMURL: https://research.aalto.fi/en/publications/277a0097-e13b-4bc3-bc2d-4ec67be00f40en_US
dc.identifier.otherPURE LINK: http://www.scopus.com/inward/record.url?scp=84959513462&partnerID=8YFLogxKen_US
dc.identifier.otherPURE FILEURL: https://research.aalto.fi/files/80695336/Antonov_All_Digital_Phase_Locked_IEEE.pdfen_US
dc.identifier.urihttps://aaltodoc.aalto.fi/handle/123456789/113379
dc.identifier.urnURN:NBN:fi:aalto-202203162258
dc.language.isoenen
dc.relation.ispartofEuropean Conference on Circuit Theory and Designen
dc.relation.ispartofseries2015 European Conference on Circuit Theory and Design, ECCTD 2015en
dc.rightsopenAccessen
dc.subject.keywordCMOS digital integrated circuitsen_US
dc.subject.keywordcalibrationen_US
dc.subject.keyworddigital phase locked loopsen_US
dc.subject.keywordoptimisationen_US
dc.subject.keywordADPLL phase accumulator speed optimizationen_US
dc.subject.keywordCMOSen_US
dc.subject.keywordMIPI M-PHY serial link transmitteren_US
dc.subject.keywordPVT calibrationen_US
dc.subject.keywordall-digital phase-locked loopen_US
dc.subject.keywordclock generatoren_US
dc.subject.keywordfrequency 1.2 GHz to 5.8 GHzen_US
dc.subject.keywordloop type changing criteriaen_US
dc.subject.keywordphase digitization processen_US
dc.subject.keywordpower savingen_US
dc.subject.keywordsize 40 nmen_US
dc.subject.keywordCMOS integrated circuitsen_US
dc.subject.keywordClocksen_US
dc.subject.keywordDelaysen_US
dc.subject.keywordMonitoringen_US
dc.subject.keywordPhase locked loopsen_US
dc.subject.keywordPipeline processingen_US
dc.subject.keywordTransmittersen_US
dc.titleAll-digital phase-locked loop in 40 nm CMOS for 5.8 Gbps serial link transmitteren
dc.typeConference article in proceedingsfi
dc.type.versionacceptedVersion
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