All-digital phase-locked loop in 40 nm CMOS for 5.8 Gbps serial link transmitter
dc.contributor | Aalto-yliopisto | fi |
dc.contributor | Aalto University | en |
dc.contributor.author | Antonov, Yury | en_US |
dc.contributor.author | Tikka, Tero | en_US |
dc.contributor.author | Stadius, Kari | en_US |
dc.contributor.author | Ryynänen, Jussi | en_US |
dc.contributor.department | Department of Micro and Nanosciences | en |
dc.contributor.groupauthor | Jussi Ryynänen Group | en |
dc.date.accessioned | 2022-03-16T12:51:49Z | |
dc.date.available | 2022-03-16T12:51:49Z | |
dc.date.issued | 2015-10-16 | en_US |
dc.description.abstract | This paper describes an all-digital phase-locked loop based clock generator for a MIPI M-PHY serial link transmitter. The paper focuses on ADPLL phase accumulator speed optimization, PVT calibration, loop type changing criteria and power saving in phase digitization process. The experimental circuit is implemented in 40 nm CMOS and generates the MIPI M-PHY defined frequencies from 1.2 GHz to 5.8 GHz. | en |
dc.description.version | Peer reviewed | en |
dc.format.mimetype | application/pdf | en_US |
dc.identifier.citation | Antonov, Y, Tikka, T, Stadius, K & Ryynänen, J 2015, All-digital phase-locked loop in 40 nm CMOS for 5.8 Gbps serial link transmitter . in 2015 European Conference on Circuit Theory and Design, ECCTD 2015 ., 7300035, IEEE, European Conference on Circuit Theory and Design, Trondheim, Norway, 24/08/2015 . https://doi.org/10.1109/ECCTD.2015.7300035 | en |
dc.identifier.doi | 10.1109/ECCTD.2015.7300035 | en_US |
dc.identifier.isbn | 978-1-4799-9877-7 | |
dc.identifier.isbn | 978-1-4799-9876-0 | |
dc.identifier.other | PURE UUID: 277a0097-e13b-4bc3-bc2d-4ec67be00f40 | en_US |
dc.identifier.other | PURE ITEMURL: https://research.aalto.fi/en/publications/277a0097-e13b-4bc3-bc2d-4ec67be00f40 | en_US |
dc.identifier.other | PURE LINK: http://www.scopus.com/inward/record.url?scp=84959513462&partnerID=8YFLogxK | en_US |
dc.identifier.other | PURE FILEURL: https://research.aalto.fi/files/80695336/Antonov_All_Digital_Phase_Locked_IEEE.pdf | en_US |
dc.identifier.uri | https://aaltodoc.aalto.fi/handle/123456789/113379 | |
dc.identifier.urn | URN:NBN:fi:aalto-202203162258 | |
dc.language.iso | en | en |
dc.relation.ispartof | European Conference on Circuit Theory and Design | en |
dc.relation.ispartofseries | 2015 European Conference on Circuit Theory and Design, ECCTD 2015 | en |
dc.rights | openAccess | en |
dc.subject.keyword | CMOS digital integrated circuits | en_US |
dc.subject.keyword | calibration | en_US |
dc.subject.keyword | digital phase locked loops | en_US |
dc.subject.keyword | optimisation | en_US |
dc.subject.keyword | ADPLL phase accumulator speed optimization | en_US |
dc.subject.keyword | CMOS | en_US |
dc.subject.keyword | MIPI M-PHY serial link transmitter | en_US |
dc.subject.keyword | PVT calibration | en_US |
dc.subject.keyword | all-digital phase-locked loop | en_US |
dc.subject.keyword | clock generator | en_US |
dc.subject.keyword | frequency 1.2 GHz to 5.8 GHz | en_US |
dc.subject.keyword | loop type changing criteria | en_US |
dc.subject.keyword | phase digitization process | en_US |
dc.subject.keyword | power saving | en_US |
dc.subject.keyword | size 40 nm | en_US |
dc.subject.keyword | CMOS integrated circuits | en_US |
dc.subject.keyword | Clocks | en_US |
dc.subject.keyword | Delays | en_US |
dc.subject.keyword | Monitoring | en_US |
dc.subject.keyword | Phase locked loops | en_US |
dc.subject.keyword | Pipeline processing | en_US |
dc.subject.keyword | Transmitters | en_US |
dc.title | All-digital phase-locked loop in 40 nm CMOS for 5.8 Gbps serial link transmitter | en |
dc.type | A4 Artikkeli konferenssijulkaisussa | fi |
dc.type.version | acceptedVersion |