All-digital phase-locked loop in 40 nm CMOS for 5.8 Gbps serial link transmitter
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A4 Artikkeli konferenssijulkaisussa
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2015 European Conference on Circuit Theory and Design, ECCTD 2015
Abstract
This paper describes an all-digital phase-locked loop based clock generator for a MIPI M-PHY serial link transmitter. The paper focuses on ADPLL phase accumulator speed optimization, PVT calibration, loop type changing criteria and power saving in phase digitization process. The experimental circuit is implemented in 40 nm CMOS and generates the MIPI M-PHY defined frequencies from 1.2 GHz to 5.8 GHz.Description
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CMOS digital integrated circuits, calibration, digital phase locked loops, optimisation, ADPLL phase accumulator speed optimization, CMOS, MIPI M-PHY serial link transmitter, PVT calibration, all-digital phase-locked loop, clock generator, frequency 1.2 GHz to 5.8 GHz, loop type changing criteria, phase digitization process, power saving, size 40 nm, CMOS integrated circuits, Clocks, Delays, Monitoring, Phase locked loops, Pipeline processing, Transmitters
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Citation
Antonov, Y, Tikka, T, Stadius, K & Ryynänen, J 2015, All-digital phase-locked loop in 40 nm CMOS for 5.8 Gbps serial link transmitter. in 2015 European Conference on Circuit Theory and Design, ECCTD 2015., 7300035, IEEE, European Conference on Circuit Theory and Design, Trondheim, Norway, 24/08/2015. https://doi.org/10.1109/ECCTD.2015.7300035