Time-domain simulation of reduced-order interconnect models

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Volume Title

Helsinki University of Technology | Diplomityö
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Authors

Date

2002

Department

Sähkö- ja tietoliikennetekniikan osasto

Major/Subject

Teoreettinen sähkötekniikka

Mcode

S-55

Degree programme

Language

en

Pages

vii + 35 s. + liitt. 9

Series

Description

Supervisor

Valtonen, Martti

Thesis advisor

Roos, Janne

Keywords

circuit simulation, piirisimulointi, interconnect simulation, interconnect-simulointi, model reduction, malliredusointi, frequency-domain model, taajuusalueen malli, transient analysis, transienttianalyysi, APLAC

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Citation

Permanent link to this item

https://urn.fi/URN:NBN:fi:aalto-2020120449072

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[dipl] Teknillinen korkeakoulu / TKK