Time-domain simulation of reduced-order interconnect models
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Journal Title
Journal ISSN
Volume Title
Helsinki University of Technology |
Diplomityö
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Instructions for the author
Author
Date
2002
Department
Major/Subject
Teoreettinen sähkötekniikka
Mcode
S-55
Degree programme
Language
en
Pages
vii + 35 s. + liitt. 9
Series
Description
Supervisor
Valtonen, MarttiThesis advisor
Roos, JanneKeywords
circuit simulation, piirisimulointi, interconnect simulation, interconnect-simulointi, model reduction, malliredusointi, frequency-domain model, taajuusalueen malli, transient analysis, transienttianalyysi, APLAC
