A study on low power PVT-robust delay locked loop: A subthreshold DLL-based clock generator with 90° I/Q signals for pulse-injection crystal oscillator application

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School of Electrical Engineering | Master's thesis

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Mcode

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en

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52

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Abstract

This paper presents the design of an ultra-low-power, Process, Voltage, and Temperature (PVT)-robust Delay-Locked Loop (DLL) based clock generator. The system is implemented in a 130 nm Complementary Metal–Oxide–Semiconductor (CMOS) process to generate 32.768 kHz In-phase/Quadrature (I/Q) clock signals for a Pulse-Injection Crystal Oscillator (PIXO) application. To achieve minimal power consumption, the entire circuit operates in the subthreshold region. The design addresses the significant challenge of device mismatch inherent in subthreshold operation through careful circuit topology choices and layout techniques. The proposed architecture includes a clock slicer using area-efficient series-parallel current mirrors, a supply-independent adaptive bias generator, and a novel Charge Pump (CP)-integrated quadrature Phase Detector (PD) that eliminates charge-coupling-induced current spikes. Simulation results demonstrate a total power consumption of 553.39 nW at 1.25 V at room temperature. The DLL achieves a startup time of 300 μs and maintains delay-time variations within –5.5% to +1% across a supply range of 1.1 V to 1.4 V and a temperature range of –40 °C to 90 °C, as well as ±18% (3σ) in Monte Carlo (MC) mismatch simulations, meeting the requirements for the target application.

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Supervisor

Kim, Kwantae

Thesis advisor

Sillanpää, Tero

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