Ultra-Low-Power Wake-up Clock Design for SoC Applications

Loading...
Thumbnail Image
Journal Title
Journal ISSN
Volume Title
Perustieteiden korkeakoulu | Master's thesis
Date
2019-10-21
Department
Major/Subject
Embedded Systems
Mcode
SCI3024
Degree programme
Master's Programme in ICT Innovation
Language
en
Pages
53 + 7
Series
Abstract
This thesis studies how to design an ultra-low-power wake-up clock circuit for SoCapplications that essentially consists of a resistor based reference circuit, switched-capacitor branch, an ultra-low-power amplifier, a VCO and a non-overlapping clockphase generator circuit. The circuit is designed in 180-nm CMOS technology usingCAD software for circuit design, layout design, pre and post-layout simulations.At first, a brief study of different clock-generation circuit architectures is made,wherein their merits and de-merits are discussed. This is followed by a study ofan ultra-low-power amplifier, ring-oscillator-based VCO, non-overlapping clockcircuits, the bias generation circuit and the current reference circuit. Additionally,a reference current chopping technique that further improves temperature stabilityis also described. Later, the report discusses the design and simulations of theactual implementation. Analysis of the design with regards to power consumption,temperature stability and layout area are carried out. The circuit operates at8.254kHz consuming 70.4nW with a temperature stability of 7.35ppm/◦C in thetemperature range of -40◦C to 75◦C. The final layout takes an area of 0.153mm2.The final design is analysed for its functionality at various process, voltage andtemperature corners. Future improvements in the current design are also discussedat the end of this report.
Description
Supervisor
Halonen, Kari
Thesis advisor
Salomaa, Jarno
Keywords
ultra-low-power, clock design, wake-up timer, low temperature coefficient, frequency locked loop
Other note
Citation