Title: | Building blocks for fast circuit simulation Nopean piirisimuloinnin rakennuspalikoita |
Author(s): | Honkala, Mikko |
Date: | 2012 |
Language: | en |
Pages: | 75 + app. 82 |
Department: | Radiotieteen ja -tekniikan laitos Department of Radio Science and Engineering |
ISBN: | 978-952-60-4923-6 (electronic) 978-952-60-4922-9 (printed) |
Series: | Aalto University publication series DOCTORAL DISSERTATIONS, 174/2012 |
ISSN: | 1799-4942 (electronic) 1799-4934 (printed) 1799-4934 (ISSN-L) |
Supervising professor(s): | Valtonen, Martti, Prof., Aalto University, Finland |
Thesis advisor(s): | Roos, Janne, D.Sc. (Tech.), Aalto University, Finland |
Subject: | Electrical engineering |
Keywords: | circuit simulation, numerical analysis, parallel processing, iterative methods, model-order reduction, preconditioners, Piirisimulointi, numeerinen analyysi, rinnakkaislaskenta, iteratiiviset menetelmät, malliredusointi, pohjustimetnaeos, nulla |
|
|
Abstract:Nykyaikaiset elektroniikkapiirit ovat tyypillisesti isoja, tuhansien transistorien kokonaisuuksia. Suunnitteluprosessin aikana niiden toiminta pitää tarkastaa laskennallisesti haastavien simulaatioiden avulla. Näin ollen nopeille ja tarkoille simulaatiotyökaluille on tarvetta. |
|
Parts:[Publication 1]: M. Honkala. Nonmonotone norm-reduction method for circuit simulation. Electronics Letters, vol. 38, pp. 1316–1317, Oct. 2002.[Publication 2]: M. Honkala, J. Roos, and V. Karanko. On nonlinear iteration methods for DC analysis of industrial circuits. Mathematics in Industry 8: Progress in Industrial Mathematics at ECMI 2004, (A. D. Bucchianico, R. M. M. Mattheij, and M. A. Peletier, eds.), pp. 144–148, 2006.[Publication 3]: M. Honkala, J. Roos, and M. Valtonen. New multilevel Newton–Raphson method for parallel circuit simulation. Proceedings of European Conference on Circuit Theory and Design, vol. II, pp. 113–116, Aug. 2001.[Publication 4]: V. Karanko and M. Honkala. A parallel harmonic balance simulator for shared memory multicomputers. Proceedings of the 34th European Microwave Conference, pp. 849–851, 2004.[Publication 5]: M. Honkala and V. Karanko. Mixed preconditioners for harmonic balance Jacobians. International Journal of RF and Microwave Computer-Aided Engineering, vol. 19, no. 2, pp. 211–217, 2009.[Publication 6]: M. Honkala, V. Karanko, J. Roos, and M. Valtonen. Frequency/time block preconditioners for harmonic balance Jacobians. Proceedings of European Conference on Circuit Theory and Design, pp. 607–610, Aug. 2009.[Publication 7]: P. Miettinen, M. Honkala, J. Roos, C. Neff, and A. Basermann. Study and development of an efficient RC-in–RC-out MOR method. Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, pp. 1277–1280, Aug. 2008.[Publication 8]: M. Honkala, P. Miettinen, J. Roos, and C. Neff. Hierarchical modelorder reduction flow. Mathematics in Industry 14: Scientific Computing in Electrical Engineering SCEE 2008, (J. Roos and L. R. J. Costa, eds.), pp. 539–546, 2010.[Publication 9]: J. Roos, M. Honkala, and P. Miettinen. GABOR: global-approximationbased order reduction. Mathematics in Industry 14: Scientific Computing in Electrical Engineering SCEE 2008, (J. Roos and L. R. J. Costa, eds.), pp. 517–514, 2010.[Publication 10]: P. Miettinen, M. Honkala, J. Roos, and M. Valtonen. PartMOR: partitioningbased realizable model-order reduction method for RLC circuits. IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 3, pp. 374–387, 2011. |
|
|
Unless otherwise stated, all rights belong to the author. You may download, display and print this publication for Your own personal use. Commercial use is prohibited.
Page content by: Aalto University Learning Centre | Privacy policy of the service | About this site