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A Blocker-Tolerant Two-Stage Harmonic-Rejection RF Front-End

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dc.contributor Aalto-yliopisto fi
dc.contributor Aalto University en
dc.contributor.author Ul Haq, Faizan
dc.contributor.author Englund, Mikko
dc.contributor.author Antonov, Yury
dc.contributor.author Stadius, Kari
dc.contributor.author Kosunen, Marko
dc.contributor.author Östman, Kim
dc.contributor.author Koli, Kimmo
dc.contributor.author Ryynänen, Jussi
dc.date.accessioned 2020-02-12T10:48:26Z
dc.date.available 2020-02-12T10:48:26Z
dc.date.issued 2019
dc.identifier.citation Ul Haq , F , Englund , M , Antonov , Y , Stadius , K , Kosunen , M , Östman , K , Koli , K & Ryynänen , J 2019 , A Blocker-Tolerant Two-Stage Harmonic-Rejection RF Front-End . in IEEE Radio Frequency Integrated Circuits Symposium . IEEE Radio Frequency Integrated Circuits Symposium digest of papers , IEEE , pp. 203-206 , IEEE Radio Frequency Integrated Circuits Symposium , Boston , Massachusetts , United States , 02/06/2019 . https://doi.org/10.1109/RFIC.2019.8701765 en
dc.identifier.isbn 978-1-7281-1701-0
dc.identifier.issn 1529-2517
dc.identifier.issn 2375-0995
dc.identifier.other PURE UUID: 60f8f5dc-da1d-43ee-8ddf-e51206446ac7
dc.identifier.other PURE ITEMURL: https://research.aalto.fi/en/publications/a-blockertolerant-twostage-harmonicrejection-rf-frontend(60f8f5dc-da1d-43ee-8ddf-e51206446ac7).html
dc.identifier.other PURE FILEURL: https://research.aalto.fi/files/35822509/ELEC_UlHaq_Blocker_tolerant_RFICS.pdf
dc.identifier.uri https://aaltodoc.aalto.fi/handle/123456789/43078
dc.description | openaire: EC/H2020/704947/EU//ADVANTAG5
dc.description.abstract SAW-less wideband receivers need to operate linearly in the presence of strong out-of-band blockers. In this paper, we introduce a blocker tolerant harmonic rejection RF front-end which is able to suppress blockers present at the local oscillator harmonics. The suppression is achieved by applying harmonic rejection in two stages, such that the first harmonic rejection already occurs at the output of LNA. The proposed front-end achieves this harmonic rejection with simpler 6-phase LO clocking and reduced number of base-band signal paths compared to 8-phase HR architectures. Further, the proposed design does not require any precise gain coefficients and implementing the harmonic rejection in two stages makes it more mismatch tolerant. In addition, near-band blocker linearity is improved by implementing a third order base-band feedback response which acts in conjunction with N-path filtering. Implemented in a 28nm FDSOI process, the front-end demonstrate 18-37dB harmonic rejection from the first stage and around46-53dB of harmonic rejection from the second stage with a state-of-the-art blocker compression point of 2.5dBm for a third harmonic blocker and a near-band blocker compression point of -6.5dBm. en
dc.format.extent 203-206
dc.format.mimetype application/pdf
dc.language.iso en en
dc.relation info:eu-repo/grantAgreement/EC/H2020/704947/EU//ADVANTAG5
dc.relation.ispartof IEEE Radio Frequency Integrated Circuits Symposium en
dc.relation.ispartofseries IEEE Radio Frequency Integrated Circuits Symposium en
dc.relation.ispartofseries IEEE Radio Frequency Integrated Circuits Symposium digest of papers en
dc.rights openAccess en
dc.title A Blocker-Tolerant Two-Stage Harmonic-Rejection RF Front-End en
dc.type A4 Artikkeli konferenssijulkaisussa fi
dc.description.version Peer reviewed en
dc.contributor.department Jussi Ryynänen Group
dc.contributor.department Department of Electronics and Nanoengineering
dc.contributor.department Nordic Semiconductor Oy
dc.contributor.department Huawei Technologies
dc.subject.keyword Harmonic rejection
dc.subject.keyword blocker tolerance
dc.identifier.urn URN:NBN:fi:aalto-202002122147
dc.identifier.doi 10.1109/RFIC.2019.8701765
dc.type.version acceptedVersion


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