Integrated Radio-Frequency Receivers for RF-to-Digital Converters

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dc.contributor Aalto-yliopisto fi
dc.contributor Aalto University en
dc.contributor.advisor Stadius, Kari, Dr., Aalto University, Department of Electronics and Nanoengineering, Finland
dc.contributor.author Ul Haq, Faizan
dc.date.accessioned 2019-10-09T09:01:27Z
dc.date.available 2019-10-09T09:01:27Z
dc.date.issued 2019
dc.identifier.isbn 978-952-60-8719-1 (electronic)
dc.identifier.isbn 978-952-60-8718-4 (printed)
dc.identifier.issn 1799-4942 (electronic)
dc.identifier.issn 1799-4934 (printed)
dc.identifier.issn 1799-4934 (ISSN-L)
dc.identifier.uri https://aaltodoc.aalto.fi/handle/123456789/40622
dc.description.abstract The widespread usage of mobile communication in recent decades has crowded the frequency spectrum with multiple bands and communication standards. An ideal wireless receiver for such a scenario will need to cover all frequency bands/standards with the possibility of instant reconfigurability through software control. The receiver should also be entirely integrated to gain the advantages of mobility and cheaper production costs. The ultimate goal of an ideal receiver is encapsulated in the concept of software-defined radio (SDR). An attractive approach to realize an SDR is an RF-to-digital converter. In best case, an RF-to-digital converter consists of an analog-to-digital converter (ADC) which is directly connected to a wideband antenna. This means that the received signal on the antenna is immediately converted in the digital domain where reconfigurability is easy to achieve. However, such a complete RF-to-digital converter has so far proved to be an elusive goal due to impractically high power consumption requirements of ADC in the GHz range. Therefore, a practical RF-to-digital converter is followed by an RF front-end which reduces the power consumption requirements of an ADC by signal amplification, filtering, and frequency down-conversion. SDR research for such a practical case is focused towards reconfigurable, wideband and digital intensive RF front-ends. It is also targetted at reducing the number of parallel receiver front-ends by implementing a single wideband and fully integrated front-end capable of receiving all frequency bands/standards. To design receiver solutions for such a practical RF-to-digital converter, new techniques are needed to overcome the design challenges. This thesis focuses on finding new solutions to four of these design challenges related to the goal of RF-to-digital converters: 1) Blocker tolerance in wideband RF front-ends; 2) harmonic rejection RF-front ends with on-chip N-path filtering; 3) transmitter self leakage cancellation, and; 4) blocker rejection and sensitivity issues in direct delta sigma receivers. Starting from the detailed description of these challenges, research outcomes on both theoretical and experimental fronts are presented. In particular, a harmonic-rejection receiver was fabricated in 28nm fully-depleted silicon-on-insulator (FDSOI) technology. The receiver attempts to resolve many of the above-mentioned challenges through higher-order on-chip filtering, simple local-oscillator clocking, and a two-stage harmonic-rejection implementation. The receiver front-end also includes a novel transmitter signal-leakage cancellation technique through buried-gate signaling in an FDSOI process. In addition to the fabricated receiver, the thesis incorporates two new blocker attenuation techniques at the input of the low-noise amplifier in the receiver chain. On the theoretical front, sensitivity issues in direct delta sigma receivers are analyzed with detailed theoretical modeling leading to simple design guidelines. Details of all these contributions can be found in the author's publications I-IX. en
dc.format.extent 209
dc.format.mimetype application/pdf en
dc.language.iso en en
dc.publisher Aalto University en
dc.publisher Aalto-yliopisto fi
dc.relation.ispartofseries Aalto University publication series DOCTORAL DISSERTATIONS en
dc.relation.ispartofseries 167/2019
dc.relation.haspart [Publication 1]: F. Ul Haq, M. Englund, K. Stadius, M. Kosunen, K.B. Östman, K. Koli, J. Ryynänen. A wideband blocker resilient RF front-end with selective input-impedance matching for direct delta sigma receiver architectures. In IEEE NORCAS Conference, pp. 1-4, Copenhagen, Denmark, November 2016. DOI: 10.1109/NORCHIP.2016.7792880
dc.relation.haspart [Publication 2]: F. Ul Haq, M. Englund, K. Stadius, M. Kosunen, K.B. Östman, K. Koli, J. Ryynänen. A wideband blocker resilient direct delta sigma receiver with selective input-impedance matching. In IEEE ISCAS Conference, pp. 1-4, Baltimore, MD USA, May 2017. DOI: 10.1109/ISCAS.2017.8050249
dc.relation.haspart [Publication 3]: F. Ul Haq, M. Englund, Y. Antonov, K. Stadius, M. Kosunen, K.B. Östman, K. Koli, J. Ryynänen. Full-duplex wireless transceiver self-interference cancellation through FD-SOI buried-gate signaling. In IEEE ISCAS Conference, pp. 1-5, Florence, Italy, May 2018. DOI: 10.1109/ISCAS.2018.8351823
dc.relation.haspart [Publication 4]: F. Ul Haq, M. Englund, Y. Antonov, K. Stadius, M. Kosunen, K.B. Östman, K. Koli, J. Ryynänen. A blocker-tolerant two-stage harmonic-rejection RF front-End. In IEEE RFIC symposium, Boston, USA, June 2019
dc.relation.haspart [Publication 5]: F. Ul Haq, K.B. Östman, M. Englund, K. Stadius, M. Kosunen, K. Koli, J. Ryynänen. A common-gate common-source low noise amplifier based RF front-end with selective input impedance matching for blocker-resilient receivers. Wiley journal of circuit theory and applications, 2018, pp. 1427-1442, Vol. 46, Issue 8. Full text in Acris/Aaltodoc: http://urn.fi/URN:NBN:fi:aalto-201806183309. DOI: 10.1002/cta.2473
dc.relation.haspart [Publication 6]: F. Ul Haq, M. Englund, K. Stadius, M. Kosunen, K.B. Östman, K. Koli, J. Ryynänen. Quantization noise upconversion effects in mixer first direct delta-sigma receivers. Accepted for publication in Wiley journal of circuit theory and applications, 2019
dc.relation.haspart [Publication 7]: M. Englund, F. Ul Haq, K. Stadius, M. Kosunen, K.B. Östman, K. Koli, J. Ryynänen. A systematic design method for direct delta-sigma receivers. IEEE transactions on Circuits and Systems I, pp. 2389-2402, Vol. 65, Issue. 8, August 2018. Full text in Acris/Aaltodoc: http://urn.fi/URN:NBN:fi:aalto-201901301390. DOI: 10.1109/TCSI.2017.2777895
dc.relation.haspart [Publication 8]: F. Ul Haq, M. Englund, Y. Antonov, M. Tenhunen, K. Stadius, M. Kosunen, K.B. Östman, K. Koli, J. Ryynänen. A blocker-tolerant two-stage harmonic-rejection receiver. Submitted to IEEE transcations on Microwave theory and techniques, 2019.
dc.relation.haspart [Publication 9]: F. Ul Haq, M. Englund, K. Stadius, M. Kosunen, K.B. Östman, K. Koli, J. Ryynänen. A wideband blocker resilient direct delta sigma receiver with selective input-impedance matching. Submitted to Springer journal of analog integrated circuits and signal processing, 2019
dc.subject.other Electrical engineering en
dc.title Integrated Radio-Frequency Receivers for RF-to-Digital Converters en
dc.type G5 Artikkeliväitöskirja fi
dc.contributor.school Sähkötekniikan korkeakoulu fi
dc.contributor.school School of Electrical Engineering en
dc.contributor.department Elektroniikan ja nanotekniikan laitos fi
dc.contributor.department Department of Electronics and Nanoengineering en
dc.subject.keyword wireless en
dc.subject.keyword wireless receiver en
dc.subject.keyword radio-requency receiver en
dc.subject.keyword RF-to-digital en
dc.subject.keyword converter en
dc.subject.keyword software-defined radio en
dc.identifier.urn URN:ISBN:978-952-60-8719-1
dc.type.dcmitype text en
dc.type.ontasot Doctoral dissertation (article-based) en
dc.type.ontasot Väitöskirja (artikkeli) fi
dc.contributor.supervisor Ryynänen, Jussi, Prof., Aalto University, Department of Electronics and Nanoengineering, Finland
dc.opn Wisland, Dag T., Prof., University of Oslo, Norway
dc.rev Neviani, Andrea, Prof., University of Padua, Italy
dc.rev Zito, Domenico, Prof., Aarhus University, Denmark
dc.date.defence 2019-10-17


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