Bordered Block-Diagonal Preserved Model-Order Reduction for RLC Circuits

Xu, Lei

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dc.contributor	Aalto-yliopisto	fi
dc.contributor	Aalto University	en
dc.contributor.advisor	Honkala, Mikko
dc.contributor.author	Xu, Lei
dc.date.accessioned	2012-07-02T08:25:54Z
dc.date.available	2012-07-02T08:25:54Z
dc.date.issued	2011
dc.identifier.uri	https://aaltodoc.aalto.fi/handle/123456789/3723
dc.description.abstract	This thesis details the research of the bordered block-diagonal preserved model-order reduction (BVOR) method and implementation of the corresponding tool designed for facilitating the simulation of industrial, very large sized linear circuits or linear sub-circuits of a nonlinear circuit. The BVOR tool is able to extract the linear RLC parts of the circuit from any given typical SPICE netlist and perform reduction using an appropriate algorithm for optimum efficiency. The implemented algorithms in this tool are bordered block-diagonal matrix solver and bordered block-diagonal matrix based block Arnoldi method.	en
dc.format.extent	[8] + 40
dc.format.mimetype	application/pdf
dc.language.iso	en	en
dc.publisher	Aalto University	en
dc.publisher	Aalto-yliopisto	fi
dc.title	Bordered Block-Diagonal Preserved Model-Order Reduction for RLC Circuits	en
dc.type	G2 Pro gradu, diplomityö	fi
dc.contributor.department	Radiotieteen ja -tekniikan laitos	fi
dc.subject.keyword	bordered block-diagonal preserved model-order reduction	en
dc.subject.keyword	RLC circuits	en
dc.subject.keyword	circuit simulation	en
dc.identifier.urn	URN:NBN:fi:aalto-201207022689
dc.type.dcmitype	text	en
dc.programme.major	Teoreettinen sähkötekniikka	fi
dc.programme.mcode	S-55
dc.type.ontasot	Diplomityö	fi
dc.type.ontasot	Master's thesis	en
dc.contributor.supervisor	Valtonen, Martti
dc.location	P1	fi
local.aalto.openaccess	yes
local.aalto.digifolder	Aalto_89745
dc.rights.accesslevel	openAccess
local.aalto.idinssi	42730
dc.type.publication	masterThesis
dc.type.okm	G2 Pro gradu, diplomityö

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