Power-Scalable Dynamic Element Matching for a 3.4-GHz 9-bit ΔΣ RF-DAC in 16-nm FinFET

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dc.contributor Aalto-yliopisto fi
dc.contributor Aalto University en
dc.contributor.author Roverato, E.
dc.contributor.author Kosunen, M.
dc.contributor.author Cornelissens, K.
dc.contributor.author Korhonen, T.
dc.contributor.author Samsom, H.
dc.contributor.author Borremans, M.
dc.contributor.author Ryynänen, J.
dc.date.accessioned 2018-12-10T10:17:26Z
dc.date.available 2018-12-10T10:17:26Z
dc.date.issued 2018
dc.identifier.citation Roverato , E , Kosunen , M , Cornelissens , K , Korhonen , T , Samsom , H , Borremans , M & Ryynänen , J 2018 , ' Power-Scalable Dynamic Element Matching for a 3.4-GHz 9-bit ΔΣ RF-DAC in 16-nm FinFET ' IEEE Solid State Circuits Letters , vol. 1 , no. 5 , pp. 126-129 . DOI: 10.1109/LSSC.2018.2875823 en
dc.identifier.issn 2573-9603
dc.identifier.other PURE UUID: 530457cb-38fd-4ba3-8108-237770c2f048
dc.identifier.other PURE ITEMURL: https://research.aalto.fi/en/publications/powerscalable-dynamic-element-matching-for-a-34ghz-9bit--rfdac-in-16nm-finfet(530457cb-38fd-4ba3-8108-237770c2f048).html
dc.identifier.other PURE FILEURL: https://research.aalto.fi/files/29768934/ELEC_roverato_et_al_power_scalable_IEEESSCL.pdf
dc.identifier.uri https://aaltodoc.aalto.fi/handle/123456789/35046
dc.description.abstract This letter presents a hardware-efficient technique to scale the power consumption of dynamic element matching (DEM) DACs with the static back-off level of the digital input signal. Unlike previous DEM techniques, the proposed power-scalable approach disables parts of the DEM encoder and DAC elements when the digital signal level is decreased from full-scale, thus resulting in reduced power consumption and lower mismatch noise at the DAC output. Power-scalable DEM is particularly useful in digital-intensive RF transmitters, where 30–50 dB of signal power control may be performed in the digital domain. The concept is demonstrated for a 3.4-GHz 9-bit I/Q RF-DAC, utilizing bandpass delta–sigma modulation and DEM with programmable center frequency. The circuit is fabricated in a 16-nm FinFET process. When changing the digital back-off level of an LTE20 carrier from 0 to −18 dB, measurement results show a 72% reduction in total power consumption and 4.5-dB lower mismatch noise, achieved without performing any biastuning or gain control in the analog domain. The digital delta–sigma modulator and DEM encoder consume less than 20 mW in full-scale mode. en
dc.format.extent 4
dc.format.extent 126-129
dc.format.mimetype application/pdf
dc.language.iso en en
dc.relation.ispartofseries IEEE Solid State Circuits Letters en
dc.relation.ispartofseries Volume 1, issue 5 en
dc.rights openAccess en
dc.subject.other 213 Electronic, automation and communications engineering, electronics en
dc.title Power-Scalable Dynamic Element Matching for a 3.4-GHz 9-bit ΔΣ RF-DAC in 16-nm FinFET en
dc.type A1 Alkuperäisartikkeli tieteellisessä aikakauslehdessä fi
dc.description.version Peer reviewed en
dc.contributor.department Department of Electronics and Nanoengineering
dc.contributor.department Huawei Technologies
dc.subject.keyword Modulation
dc.subject.keyword Power demand
dc.subject.keyword Solid state circuits
dc.subject.keyword Gain control
dc.subject.keyword Multiplexing
dc.subject.keyword Radio frequency
dc.subject.keyword Radio transmitters
dc.subject.keyword Delta–sigma modulation
dc.subject.keyword digital gain control
dc.subject.keyword dynamic element matching (DEM)
dc.subject.keyword power back-off
dc.subject.keyword RF-DAC
dc.subject.keyword 213 Electronic, automation and communications engineering, electronics
dc.identifier.urn URN:NBN:fi:aalto-201812106061
dc.identifier.doi 10.1109/LSSC.2018.2875823
dc.type.version acceptedVersion

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