Analysis of Nonidealities in Undersampling SAR ADCs

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dc.contributor Aalto-yliopisto fi
dc.contributor Aalto University en
dc.contributor.advisor Unnikrishnan, Vishnu
dc.contributor.author Mattersdorfer, Clemens
dc.date.accessioned 2018-09-03T12:38:45Z
dc.date.available 2018-09-03T12:38:45Z
dc.date.issued 2018-08-20
dc.identifier.uri https://aaltodoc.aalto.fi/handle/123456789/33725
dc.description.abstract With the foreseeable adaptation of 5 G networks and its increasing use, blockers are becoming more common on their frequency bands. This gives rise to the need of wideband blocker-detection circuits for frequencies up to 6 GHz. The use of under- sampling SAR ADCs to detect blockers has already been demonstrated [1], however the performance showed to be lower than expected. The objective of this work is to investigate nonidealities appearing in SAR ADCs, when used as under-sampling converter. Therefore, a behavioral model of a SAR ADC has been built in Verilog-A, and an accompanying toolchain in Matlab has been devel- oped to assess the impact of system parameter variations on the dynamic performance figures (SNR, SNDR,...). The utilization of a behavioral model also allows an isolated view on otherwise interdependent phenomena, besides reducing the simulation time. System simulations show the effect of various system parameter variations on the converter performance. The conclusions drawn from behavioral simulations have been verified by inserting 65 nm technology transistors into the behavioral model. The sampling error appearing at slow switch transition times has also been investigated. It has been concluded, that the SAR ADC performance is primarily limited by the track-and-hold circuit, as the finite transition time from track- to hold-state causes the fast changing input signal to be averaged nonlinearly, instead of being sampled almost ideally. en
dc.format.extent 50+35
dc.language.iso en en
dc.title Analysis of Nonidealities in Undersampling SAR ADCs en
dc.contributor.school Sähkötekniikan korkeakoulu fi
dc.subject.keyword undersampling en
dc.subject.keyword sar adc en
dc.subject.keyword nonidealities en
dc.subject.keyword behavioral modeling en
dc.subject.keyword Verilog-A en
dc.identifier.urn URN:NBN:fi:aalto-201809034850
dc.programme.major Micro- and Nanoelectronic Circuit Design fi
dc.programme.mcode ELEC3036 fi
dc.contributor.supervisor Ryynänen, Jussi
dc.programme NanoRad - Master’s Programme in Nano and Radio Sciences fi
dc.location P1 fi
local.aalto.electroniconly yes
local.aalto.openaccess no


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