dc.contributor | Aalto-yliopisto | fi |
dc.contributor | Aalto University | en |
dc.contributor.author | Koskinen, Lauri | |
dc.date.accessioned | 2012-02-17T07:26:27Z | |
dc.date.available | 2012-02-17T07:26:27Z | |
dc.date.issued | 2005-12-16 | |
dc.identifier.isbn | 951-22-7959-2 | |
dc.identifier.issn | 1455-8440 | |
dc.identifier.uri | https://aaltodoc.aalto.fi/handle/123456789/2649 | |
dc.description.abstract | This thesis deals with Cellular Nonlinear Network (CNN) analog parallel processor networks and their implementations in current video coding standards. The target applications are low-power video encoders within 3rd generation mobile terminals. The video codecs of such mobile terminals are defined by either the MPEG-4/H.263 or H.264 video standard. All of these standards are based on the block-based hybrid approach. As block-based motion estimation (ME) is responsible for most of the power consumption of such hybrid video encoders, this thesis deals mostly with low-power ME implementations. Low-power solutions are introduced at both the algorithmic and hardware levels. On the algorithmic level, the introduced implementations are derived from a segmentation algorithm, which has previously been partly realized. The first introduced algorithm reduces the computational complexity of ME within an object-based MPEG-4 encoder. The use of this algorithm enables a 60% drop in the power consumption of Full Search ME. The second algorithm calculates a near-optimal block-size partition for H.264 motion estimation. With this algorithm, the use of computationally complex Lagrange optimization in H.264 ME is not required. The third algorithm reduces the shape bit-rate of an object-based MPEG-4 encoder. On the hardware level a CNN-type ME architecture is introduced. The architecture includes connections and circuitry to fully realize block-based ME. The analog ME implemented with this architecture is capable of lower power than comparable digital realizations. A 9×9 test chip has also been realized. Additionally implemented is a digital predictive ME realization that takes advantage of the introduced partition algorithm. Although the IC layout of the ME algorithm was drawn, the design was verified as an FPGA. | en |
dc.format.extent | 133 | |
dc.format.mimetype | application/pdf | |
dc.language.iso | en | en |
dc.publisher | Helsinki University of Technology | en |
dc.publisher | Teknillinen korkeakoulu | fi |
dc.relation.ispartofseries | Report / Helsinki University of Technology, Department of Electrical and Communications Engineering, Electronic Circuit Design Laboratory | en |
dc.relation.ispartofseries | 41 | en |
dc.subject.other | Electrical engineering | en |
dc.title | Analog parallel processor solutions for video encoding | en |
dc.type | G4 Monografiaväitöskirja | fi |
dc.description.version | reviewed | en |
dc.contributor.department | Department of Electrical and Communications Engineering | en |
dc.contributor.department | Sähkö- ja tietoliikennetekniikan osasto | fi |
dc.subject.keyword | motion estimation | en |
dc.subject.keyword | cellular neural/nonlinear networks | en |
dc.subject.keyword | MPEG-4 | en |
dc.subject.keyword | H.264 | en |
dc.subject.keyword | parallel processing | en |
dc.identifier.urn | urn:nbn:fi:tkk-006093 | |
dc.type.dcmitype | text | en |
dc.type.ontasot | Väitöskirja (monografia) | fi |
dc.type.ontasot | Doctoral dissertation (monograph) | en |
dc.contributor.lab | Electronic Circuit Design Laboratory | en |
dc.contributor.lab | Piiritekniikan laboratorio | fi |
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