Title: | Applications of reprogrammability in algorithm acceleration |
Author(s): | Tommiska, Matti |
Date: | 2005-03-18 |
Language: | en |
Pages: | 119, [56] |
Department: | Department of Electrical and Communications Engineering Sähkö- ja tietoliikennetekniikan osasto |
ISBN: | 951-22-7527-9 |
Series: | Report / Helsinki University of Technology, Signal Processing Laboratory, 50 |
ISSN: | 1458-6401 |
Subject: | Electrical engineering |
Keywords: | reprogrammable logic, field programmable gate arrays, digital design, genetic algorithms, communications protocols, digital signal processing, hardware arithmetic, cryptographic implementations |
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Abstract:This doctoral thesis consists of an introductory part and eight appended publications, which deal with hardware-based reprogrammability in algorithm acceleration with a specific emphasis on the possibilities offered by modern large-scale Field Programmable Gate Arrays (FPGAs) in computationally demanding applications.
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Parts:M. Tommiska and J. Vuori. 1996. Hardware implementation of GA. In: Proceedings of the 2nd Nordic Workshop on Genetic Algorithms. Vaasa, Finland, 19-23 August 1996, pages 71-78. [article1.pdf] © 1996 by authors.M. Tommiska, M. Loukola, and T. Koskivirta. 1999. An FPGA-based implementation and simulation of the AAL type 2 receiver. Journal of Communications and Networks 1, number 1, pages 63-67. [article2.pdf] © 1999 Korean Institute of Communication Sciences (KICS). By permission.M. Tommiska. 2000. Area-efficient implementation of a fast square root algorithm. In: Proceedings of the Third IEEE International Caracas Conference on Devices, Circuits and Systems. Cancun, Mexico, 15-17 March 2000, pages S18-1 - S18-4. [article3.pdf] © 2000 IEEE. By permission.M. Tommiska and J. Skyttä. 2001. Dijkstra's shortest path routing algorithm in reconfigurable hardware. In: G. Brebner and R. Woods (editors), Proceedings of the 11th Conference on Field-Programmable Logic and Applications (FPL 2001). Belfast, Northern Ireland, UK, 27-29 August 2001, pages 653-657. [article4.pdf] © 2001 Springer-Verlag. By permission.M. Tommiska, J. Tanskanen, and J. Skyttä. 2001. Hardware-based adaptive general parameter extension in WCDMA power control. In: Proceedings of the 54th IEEE Vehicular Technology Conference (VTC 2001 Fall). Atlantic City, NJ, United States, 7-11 October 2001, volume 4, pages 2023-2027. [article5.pdf] © 2001 IEEE. By permission.A. Hämäläinen, M. Tommiska, and J. Skyttä. 2002. 6.78 gigabits per second implementation of the IDEA cryptographic algorithm. In: M. Glesner, P. Zipf, and M. Renovell (editors), Proceedings of the 12th Conference on Field-Programmable Logic and Applications (FPL 2002). Montpellier, France, 2-4 September 2002, pages 760-769. [article6.pdf] © 2002 Springer-Verlag. By permission.K. Järvinen, M. Tommiska, and J. Skyttä. 2003. A fully pipelined memoryless 17.8 Gbps AES-128 encryptor. In: Proceedings of the 11th International Symposium on Field-Programmable Gate Arrays (FPGA 2003). Monterey, CA, United States, 24-26 February 2003, pages 207-215.M. Tommiska. 2003. Efficient digital implementation of the sigmoid function for reprogrammable logic. IEE Proceedings – Computers and Digital Techniques 150, number 6, pages 403-411. [article8.pdf] © 2003 IEE. By permission. |
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