Process development and device modelling of gallium arsenide heterojunction bipolar transistors

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dc.contributor Aalto-yliopisto fi
dc.contributor Aalto University en Hovinen, Anssi 2012-02-13T12:21:56Z 2012-02-13T12:21:56Z 2001-06-01
dc.identifier.isbn 951-22-5443-3
dc.identifier.issn 0781-4984
dc.description.abstract This thesis discusses the processing and analysis of high speed semiconductor devices with emphasis on GaAs-based heterojunction bipolar transistors. The heterojunction transistor process is developed as an essential part of this thesis. Device physics is first reviewed in depth to construct a solid basis for physical one dimensional simulation of heterojunction bipolar junction transistors. Theory is then applied to a simulation platform in a way which facilitates device design and evaluation at practical level. The simulation platform was used in designing epitaxial layers for a transistor structure with heavily doped base layer and current gain target at 50. The developed transistor process relies on wet chemical isolation etching, and takes into account the restrictions that arise from the academic perspective of the processing environment. The process development goal was educational robustness. The development effort for HBT process is explained in detail, and processing steps are illustrated with scanning electron microscope images. The most critical processing steps were for defining isolation depths. Isolation is based on slow citric acid wet chemical etching monitored with a high precision profilometer. Active devices form isolated hills or "mesas" on the semi-insulating substrate. Because of the rather tall etched structures the lithography is of planarizing type. The process includes a unique double layer planarising lithography for AZ 5214E resist, developed within the framework of this thesis. The lithography is doubly functional such that it also allows two resist layers to be patterned separately on top of each other, which is utilised in defining shallow air bridges in the transistor structures. The most important measurement results are explained. Degradation of transistor performance after excessive heating or current stress is also demonstrated, and a method for processing devices with minimal amount of heating is introduced as a means to tackle the problem. Measured collector characteristics of various types of HBTs are given. Best DC characteristics were achieved with a transistor structure including non-alloyed contacts and Schottky diode collector. This thesis focused on process development and DC analysis of the transistor. Frequency characteristics were measured only for completeness. It is shown that even the non-optimized process was capable of producing transistors with power gain cut off frequency exceeding 1 GHz. en
dc.format.extent 133
dc.format.mimetype application/pdf
dc.language.iso en en
dc.publisher Helsinki University of Technology en
dc.publisher Teknillinen korkeakoulu fi
dc.relation.ispartofseries Reports in electron physics en
dc.relation.ispartofseries 2001/26 en
dc.subject.other Electrical engineering en
dc.title Process development and device modelling of gallium arsenide heterojunction bipolar transistors en
dc.type G4 Monografiaväitöskirja fi
dc.description.version reviewed en
dc.contributor.department Department of Electrical and Communications Engineering en
dc.contributor.department Sähkö- ja tietoliikennetekniikan osasto fi
dc.subject.keyword heterojunction en
dc.subject.keyword aluminum gallium arsenide en
dc.subject.keyword simulation en
dc.subject.keyword low thermal budget en
dc.subject.keyword double layer lithography en
dc.subject.keyword process development en
dc.identifier.urn urn:nbn:fi:tkk-002802
dc.type.dcmitype text en
dc.type.ontasot Väitöskirja (monografia) fi
dc.type.ontasot Doctoral dissertation (monograph) en
dc.contributor.lab Electron Physics Laboratory en
dc.contributor.lab Elektronifysiikan laboratorio fi

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