Pipeline analog-to-digital converters for wide-band wireless communications

Abstract

During the last decade, the development of the analog electronics has been dictated by the enormous growth of the wireless communications. Typical for the new communication standards has been an evolution towards higher data rates, which allows more services to be provided. Simultaneously, the boundary between analog and digital signal processing is moving closer to the antenna, thus aiming for a software defined radio. For analog-to-digital converters (ADCs) of radio receivers this indicates higher sample rate, wider bandwidth, higher resolution, and lower power dissipation.

The radio receiver architectures, showing the greatest potential to meet the commercial trends, include the direct conversion receiver and the super heterodyne receiver with an ADC sampling at the intermediate frequency (IF). The pipelined ADC architecture, based on the switched capacitor (SC) technique, has most successfully covered the widely separated resolution and sample rate requirements of these receiver architectures. In this thesis, the requirements of ADCs in both of these receiver architectures are studied using the system specifications of the 3G WCDMA standard. From the standard and from the limited performance of the circuit building blocks, design constraints for pipeline ADCs, at the architectural and circuit level, are drawn.

At the circuit level, novel topologies for all the essential blocks of the pipeline ADC have been developed. These include a dual-mode operational amplifier, low-power voltage reference circuits with buffering, and a floating-bulk bootstrapped switch for highly-linear IF-sampling. The emphasis has been on dynamic comparators: a new mismatch insensitive topology is proposed and measurement results for three different topologies are presented.

At the architectural level, the optimization of the ADCs in the single-chip direct conversion receivers is discussed: the need for small area, low power, suppression of substrate noise, input and output interfaces, etc. Adaptation of the resolution and sample rate of a pipeline ADC, to be used in more flexible multi-mode receivers, is also an important topic included. A 6-bit 15.36-MS/s embedded CMOS pipeline ADC and an 8-bit 1/15.36-MS/s dual-mode CMOS pipeline ADC, optimized for low-power single-chip direct conversion receivers with single-channel reception, have been designed.

The bandwidth of a pipeline ADC can be extended by employing parallelism to allow multi-channel reception. The errors resulted from mismatch of parallel signal paths are analyzed and their elimination is presented. Particularly, an optimal partitioning of the resolution between the stages, and the number of parallel channels, in time-interleaved ADCs are derived. A low-power 10-bit 200-MS/s CMOS parallel pipeline ADC employing double sampling and a front-end sample-and-hold (S/H) circuit is implemented.

Emphasis of the thesis is on high-resolution pipeline ADCs with IF-sampling capability. The resolution is extended beyond the limits set by device matching by using calibration, while time interleaving is applied to widen the signal bandwidth. A review of calibration and error averaging techniques is presented. A simple digital self-calibration technique to compensate capacitor mismatch within a single-channel pipeline ADC, and the gain and offset mismatch between the channels of a time-interleaved ADC, is developed. The new calibration method is validated with two high-resolution BiCMOS prototypes, a 13-bit 50-MS/s single-channel and a 14-bit 160-MS/s parallel pipeline ADC, both utilizing a highly linear front-end allowing sampling from 200-MHz IF-band.