Circuit techniques for low-voltage and high-speed A/D converters

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dc.contributor Aalto-yliopisto fi
dc.contributor Aalto University en
dc.contributor.author Waltari, Mikko
dc.date.accessioned 2012-02-10T09:22:51Z
dc.date.available 2012-02-10T09:22:51Z
dc.date.issued 2002-06-24
dc.identifier.isbn 951-22-5908-7
dc.identifier.issn 1455-8440
dc.identifier.uri https://aaltodoc.aalto.fi/handle/123456789/2186
dc.description.abstract The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage. Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented. It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes. An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock generation and buffering. The throughput of ADCs can be increased by using parallelism. This is demonstrated on the circuit level with the double-sampling technique, which is applied to S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling is presented. At the system level parallelism is utilized in a time-interleaved ADC. The mismatch of parallel signal paths produces errors, for the elimination of which a timing skew insensitive sampling circuit and a digital offset calibration are developed. A total of seven prototypes are presented: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO technique. en
dc.format.extent 276
dc.format.mimetype application/pdf
dc.language.iso en en
dc.publisher Helsinki University of Technology en
dc.publisher Teknillinen korkeakoulu fi
dc.relation.ispartofseries Report / Helsinki University of Technology, Department of Electrical and Communications Engineering, Electronic Circuit Design Laboratory en
dc.relation.ispartofseries 33 en
dc.subject.other Electrical engineering en
dc.title Circuit techniques for low-voltage and high-speed A/D converters en
dc.type G4 Monografiaväitöskirja fi
dc.description.version reviewed en
dc.contributor.department Department of Electrical and Communications Engineering en
dc.contributor.department Sähkö- ja tietoliikennetekniikan osasto fi
dc.subject.keyword analog integrated circuit en
dc.subject.keyword analog-to-digital conversion en
dc.subject.keyword BiCMOS en
dc.subject.keyword bootstrapped switch en
dc.subject.keyword CMOS en
dc.subject.keyword double-sampling en
dc.subject.keyword IF-sampling en
dc.subject.keyword low voltage en
dc.subject.keyword operational amplifier en
dc.subject.keyword pipelined analog-to-digital converter en
dc.subject.keyword sample-and-hold circuit en
dc.subject.keyword switched-capacitor en
dc.subject.keyword switched-opamp en
dc.subject.keyword time interleaving en
dc.identifier.urn urn:nbn:fi:tkk-001562
dc.type.dcmitype text en
dc.type.ontasot Väitöskirja (monografia) fi
dc.type.ontasot Doctoral dissertation (monograph) en
dc.contributor.lab Electronic Circuit Design Laboratory en
dc.contributor.lab Piiritekniikan laboratorio fi


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