Analog baseband circuits for WCDMA direct-conversion receivers

 |  Login

Show simple item record

dc.contributor Aalto-yliopisto fi
dc.contributor Aalto University en Jussila, Jarkko 2012-02-10T08:52:21Z 2012-02-10T08:52:21Z 2003-06-27
dc.identifier.isbn 951-22-6595-8
dc.identifier.issn 1455-8440
dc.description.abstract This thesis describes the design and implementation of analog baseband circuits for low-power single-chip WCDMA direct-conversion receivers. The reference radio system throughout the thesis is UTRA/FDD. The analog baseband circuit consists of two similar channels, which contain analog channel-select filters, programmable-gain amplifiers, and circuits that remove DC offsets. The direct-conversion architecture is described and the UTRA/FDD system characteristics are summarized. The UTRA/FDD specifications define the performance requirement for the whole receiver. Therefore, the specifications for the analog baseband circuit are obtained from the receiver requirements through calculations performed by hand. When the power dissipation of an UTRA/FDD direct-conversion receiver is minimized, the design parameters of an all-pole analog channel-select filter and the following Nyquist rate analog-to-digital converter must be considered simultaneously. In this thesis, it is shown that minimum power consumption is achieved with a fifth-order lowpass filter and a 15.36-MS/s Nyquist rate converter that has a 7- or 8-bit resolution. A fifth-order Chebyshev prototype with a passband ripple of 0.01 dB and a −3-dB frequency of 1.92-MHz is adopted in this thesis. The error-vector-magnitude can be significantly reduced by using a first-order 1.4-MHz allpass filter. The selected filter prototype fulfills all selectivity requirements in the analog domain. In this thesis, all the filter implementations use the opamp-RC technique to achieve insensitivity to parasitic capacitances and a high dynamic range. The adopted technique is analyzed in detail. The effect of the finite opamp unity-gain bandwidth on the filter frequency response can be compensated for by using passive methods. Compensation schemes that also track the process and temperature variations have been developed. The opamp-RC technique enables the implementation of low-voltage filters. The design and simulation results of a 1.5-V 2-MHz lowpass filter are discussed. The developed biasing scheme does not use any additional current to achieve the low-voltage operation, unlike the filter topology published previously elsewhere. Methods for removing DC offsets in UTRA/FDD direct-conversion receivers are presented. The minimum areas for cascaded AC couplings and DC-feedback loops are calculated. The distortion of the frequency response of a lowpass filter caused by a DC-feedback loop connected over the filter is calculated and a method for compensating for the distortion is developed. The time constant of an AC coupling can be increased using time-constant multipliers. This enables the implementation of AC couplings with a small silicon area. Novel time-constant multipliers suitable for systems that have a continuous reception, such as UTRA/FDD, are presented. The proposed time-constant multipliers only require one additional amplifier. In an UTRA/FDD direct-conversion receiver, the reception is continuous. In a low-power receiver, the programmable baseband gain must be changed during reception. This may produce large, slowly decaying transients that degrade the receiver performance. The thesis shows that AC-coupling networks and DC-feedback loops can be used to implement programmable-gain amplifiers, which do not produce significant transients when the gain is altered. The principles of operation, the design, and the practical implementation issues of these amplifiers are discussed. New PGA topologies suitable for continuously receiving systems have been developed. The behavior of these circuits in the presence of strong out-of-channel signals is analyzed. The interface between the downconversion mixers and the analog baseband circuit is discussed. The effect of the interface on the receiver noise figure and the trimming of mixer IIP2 are analyzed. The design and implementation of analog baseband circuits and channel-select filters for UTRA/FDD direct-conversion receivers are discussed in five application cases. The first case presents the analog baseband circuit for a chip-set receiver. A channel-select filter that has an improved dynamic range with a smaller supply current is presented next. The third and fifth application cases describe embedded analog baseband circuits for single-chip receivers. In the fifth case, the dual-mode analog baseband circuit of a quad-mode receiver designed for GSM900, DCS1800, PCS1900, and UTRA/FDD cellular systems is described. A new, highly linear low-power transconductor is presented in the fourth application case. The fourth application case also describes a channel-select filter. The filter achieves +99-dBV out-of-channel IIP2, +45-dBV out-of-channel IIP3 and 23-μVRMS input-referred noise with 2.6-mA current from a 2.7-V supply. In the fifth application case, a corresponding performance is achieved in UTRA/FDD mode. The out-of-channel IIP2 values of approximately +100 dBV achieved in this work are the best reported so far. This is also the case with the figure of merits for the analog channel-select filter and analog baseband circuit described in the fourth and fifth application cases, respectively. For equal power dissipation, bandwidth, and filter order, these circuits achieve approximately 10 dB and 15 dB higher spurious-free dynamic ranges, respectively, when compared to implementations that are published elsewhere and have the second best figure of merits. en
dc.format.extent 247
dc.format.mimetype application/pdf
dc.language.iso en en
dc.publisher Helsinki University of Technology en
dc.publisher Teknillinen korkeakoulu fi
dc.relation.ispartofseries Report / Helsinki University of Technology, Department of Electrical and Communications Engineering, Electronic Circuit Design Laboratory en
dc.relation.ispartofseries 37 en
dc.relation.haspart Additional errata file available. en
dc.subject.other Electrical engineering en
dc.title Analog baseband circuits for WCDMA direct-conversion receivers en
dc.type G4 Monografiaväitöskirja fi
dc.description.version reviewed en
dc.contributor.department Department of Electrical and Communications Engineering en
dc.contributor.department Sähkö- ja tietoliikennetekniikan osasto fi
dc.subject.keyword analog integrated circuit en
dc.subject.keyword baseband en
dc.subject.keyword BiCMOS en
dc.subject.keyword continuous time en
dc.subject.keyword direct conversion en
dc.subject.keyword highpass filter en
dc.subject.keyword lowpass filter en
dc.subject.keyword programmable gain amplifier en
dc.subject.keyword radio receiver en
dc.identifier.urn urn:nbn:fi:tkk-000683
dc.type.dcmitype text en
dc.type.ontasot Väitöskirja (monografia) fi
dc.type.ontasot Doctoral dissertation (monograph) en
dc.contributor.lab Electronic Circuit Design Laboratory en
dc.contributor.lab Piiritekniikan laboratorio fi

Files in this item

This item appears in the following Collection(s)

Show simple item record

Search archive

Advanced Search

article-iconSubmit a publication


My Account