Defect and yield analysis of semiconductor components and integrated circuits

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dc.contributor Aalto-yliopisto fi
dc.contributor Aalto University en
dc.contributor.author Karilahti, Mika
dc.date.accessioned 2012-01-24T14:38:18Z
dc.date.available 2012-01-24T14:38:18Z
dc.date.issued 2003-02-14
dc.identifier.isbn 951-22-6370-X
dc.identifier.uri https://aaltodoc.aalto.fi/handle/123456789/2053
dc.description.abstract Semiconductors were studied from the point of material, component, electrical and functional properties. Several methods were used to accomplish this, e.g. X-ray topography, etch pit analysis, statistical methods, and neural nets. The compound semiconductor components, i.e. GaAs varactor diodes, AlGaAs/InGaAs p-HEMTs, and LEDs (GaAs/AlGaAs and GaPN) were studied using the method of synchrotron X-ray topography. First, the silicon wafers studied were selected from fully processed lots with varying, though, low yields. The electrical circuits were fabricated with a CMOS (Complementary Metal-Oxide Semiconductor) process, well suited for mixed-signal applications. Then, synchrotron X-ray topographs and etch pit micrographs of the wafers were analyzed with an image processing software, written entirely for this study, to quantify the strain and defects present in the images. This information was then correlated with electrical parameters previously measured from the wafers, including the yield. Several of the parameters quantified from the synchrotron X-ray images show a strong correlation with certain measured parameters, e.g. PMOS transistor threshold voltage, polysilicon sheet resistance, N- sheet contact chain resistance. Then, some parameters practically do not correlate, e.g. NMOS breakdown voltage. A strong correlation of device yield with near-surface strain measured by synchrotron X-ray topography is found. Finally, the method of self-organizing map (SOM) neural net was applied to analyze a heartbeat rate monitor integrated circuit (IC) yield dependence on CMOS process control monitoring (PCM) data. The SOM efficiently reduces the PCM parameter space dimensions and helps in visualizing the different parameter relations. This makes it possible to identify the most probable PCM parameters affecting the yield. Those were found out to be NMOS transistor drain current and aluminum sheet resistance. en
dc.format.extent 67, [44]
dc.format.mimetype application/pdf
dc.language.iso en en
dc.publisher Helsinki University of Technology en
dc.publisher Teknillinen korkeakoulu fi
dc.relation.haspart McNally, P. J., Herbert, P. A. F., Tuomi, T., Karilahti, M. and Higgins, J. A., 1996. Analysis of the impact of dislocation distribution on the breakdown voltage of GaAs-based power varactor diodes. Journal of Applied Physics 79, pages 8294-8297.
dc.relation.haspart McNally, P. J., Tuomi, T., Herbert, P. A. F., Baric, A., Äyräs, P., Karilahti, M., Lipsanen, H. and Tromby, M., 1996. Synchrotron X-Ray Topographic Analysis of the Impact of Processing Steps on the Fabrication of AlGaAs/InGaAs p-HEMT's. IEEE Transactions on Electron Devices, Vol. 43, pages 1085-1091.
dc.relation.haspart Karilahti, M., Tuomi, T., Taskinen, M., Tulkki, J., Lipsanen, H. and McNally, P. J., 1997. Synchrotron X-ray topographic study of strain in silicon wafers with integrated circuits. Il Nuovo Cimento 19 D, pages 181-184.
dc.relation.haspart Lowney, D., McNally, P. J., O´Hare, M., Herbert, P. A. F., Perova, T., Tuomi, T., Rantamäki, R., Karilahti, M. and Danilewsky, A. N., 2001. Examination of the structural and optical failure of ultra bright LEDs under varying degrees of electrical stress using synchrotron x-ray topography and optical emission spectroscopy. J. Mater. Sci.: Materials in Electronics 12, pages 249-253.
dc.relation.haspart Karilahti, M., Tuomi, T. and McNally, P. J., 2003. Integrated circuit process control monitoring (PCM) data and wafer yield analyzed by using synchrotron X-ray topographic measurements. Semiconductor Science and Technology 18, pages 45-55.
dc.relation.haspart Karilahti, M., 2003. Neural Net Analysis of Integrated Circuit Yield Dependence on CMOS Process Control Parameters. Microelectronics Reliability 43, pages 117-121.
dc.subject.other Electrical engineering en
dc.title Defect and yield analysis of semiconductor components and integrated circuits en
dc.type G5 Artikkeliväitöskirja fi
dc.description.version reviewed en
dc.contributor.department Department of Electrical and Communications Engineering en
dc.contributor.department Sähkö- ja tietoliikennetekniikan osasto fi
dc.subject.keyword compound semiconductor en
dc.subject.keyword wafer en
dc.subject.keyword components en
dc.subject.keyword semiconductor process en
dc.subject.keyword process control monitoring en
dc.subject.keyword self-organizing map en
dc.subject.keyword integrated circuit en
dc.subject.keyword CMOS en
dc.identifier.urn urn:nbn:fi:tkk-000272
dc.type.dcmitype text en
dc.type.ontasot Väitöskirja (artikkeli) fi
dc.type.ontasot Doctoral dissertation (article-based) en
dc.contributor.lab Optoelectronics Laboratory en
dc.contributor.lab Optoelektroniikan laboratorio fi


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