Grid-voltage Synchronization Algorithms Based on Phase-locked Loop and Frequency-locked Loop for Power Converters

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dc.contributor Aalto-yliopisto fi
dc.contributor Aalto University en
dc.contributor.author Fuad, Khaled
dc.date.accessioned 2014-06-26T09:34:35Z
dc.date.available 2014-06-26T09:34:35Z
dc.date.issued 2014-06-16
dc.identifier.uri https://aaltodoc.aalto.fi/handle/123456789/13585
dc.description.abstract The purpose of this thesis is to study and find the appropriate grid-voltage synchronization method for grid-connected converters under different kinds of faults like phase unbalancing, harmonics, offset and voltage sags. The main purpose of grid-synchronization algorithms is to estimate the positive- and negative-sequence components of the utility voltage under unbalanced and distorted condition. The existing most advanced phase-locked loop (PLL) and frequency-locked loop (FLL) methods are well known method for grid-synchronization. The fundamental variable estimated by the PLL is the grid-phase angle, whereas the grid frequency is the one for the FLL. The most extended technique used for grid synchronization in three-phase three wire system is a synchronous reference frame PLL (SRF-PLL). The SRF-PLL works accurately during balanced condition, but cannot estimate voltage components during unbalanced condition. The Decoupled Double Synchronous Reference Frame PLL (DDSRF-PLL) is might be a substantiation solution for the estimation of the sequence components of the utility voltage under unbalanced condition. Another method based on the FLL, a double second-order generalized integrator FLL (DSOGI-FLL) has also the ability to detect the positive- and negative-sequence components of the utility voltage under unbalanced condition. DDSRF-PLL and DSOGI-FLL algorithms are tested under different kinds of faults and compared with each other. The results show that their performance under harmonic-distorted condition is not really acceptable. A new algorithm based on SRF-PLL, decoupled multiple synchronous reference frame PLL (DMSRF-PLL) might be a better solution for accurate detection of the positive- and negative-sequence voltage components under unbalanced and harmonic distortion condition. en
dc.format.extent 45+10
dc.format.mimetype application/pdf
dc.language.iso en en
dc.title Grid-voltage Synchronization Algorithms Based on Phase-locked Loop and Frequency-locked Loop for Power Converters en
dc.type G2 Pro gradu, diplomityö en
dc.contributor.school Sähkötekniikan korkeakoulu fi
dc.subject.keyword decoupling network en
dc.subject.keyword frequency-locked loop en
dc.subject.keyword grid-connected converter en
dc.subject.keyword phase-locked loop en
dc.subject.keyword second order generalized integrator. en
dc.identifier.urn URN:NBN:fi:aalto-201406272262
dc.programme.major Electrical Drives fi
dc.programme.mcode S3016 fi
dc.type.ontasot Diplomityö fi
dc.type.ontasot Master's thesis en
dc.contributor.supervisor Hinkkanen, Marko
dc.programme EST - Master’s Programme in Electrical Engineering fi
dc.location P1 fi


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