Process Integration of Low-Temperature Wafer-Level Microsystem Vacuum Packaging



Title:	Process Integration of Low-Temperature Wafer-Level Microsystem Vacuum Packaging
Author(s):	Stevanus, Josef
Date:	2023-08-21
Language:	en
Pages:	76
Major/Subject:	Smart Systems Integrated Solutions
Degree programme:	Master’s Programme in Smart Systems Integrated Solutions (Erasmus Mundus)
Supervising professor(s):	Vuorinen, Vesa
Thesis advisor(s):	Golim, Obert
Keywords:	solid liquid interdiffusion bonding, process integration, wafer level packaging, intermetallic compounds, hermeticity
Location:	P1 \| Archive OEV
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Permanent link to this item: http://urn.fi/URN:NBN:fi:aalto-202309035511 Email this Export to RefWorks QR Code Print BibTex Tweet