Browsing by Author "Unnikrishnan, Vishnu, Dr., Tampere University, Finland"

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  • Integrated True-Time-Delay Beamforming Receivers
    (2023) Spoof, Kalle
     School of Electrical Engineering | Doctoral dissertation (article-based)
    Advances in complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) technology have enabled the sophisticated wireless communication systems in use today. To respond to the demand for ever increasing data traffic volumes, the performance of these systems needs to improve to increase the capacity of data transfer. Beamforming is one of the technologies enabling improvements in the upcoming 5G communication systems. Beamforming with antenna arrays allows increased data throughput through spatial multiplexing, lower energy consumption through directed radio transmission and in-band spatial filtering for relaxed dynamic range and, therefore, power requirements. The often used implementation of beamforming with phased arrays limits the instantaneous bandwidth due to the use of the narrow-band approximation of propagation delay as phase shift. This bandwidth limitation can be overcome by replacing the beamforming phase shifts with true-time-delays (TTDs). Solutions for TTD beamforming are thus required to enable beamforming also for wideband radio systems. This thesis explores resampling true-time-delays as an integrated solution for beamforming receivers. The resampling TTDs are demonstrated with two prototype receiver ICs. The first prototype in 28-nm FD-SOI CMOS verified the resampling TTDs as a part of a radio frequency (RF) receiver front-end. The prototype achieved an 800 MHz instantaneous beamformed bandwidth across a 0.6--4 GHz frequency range with area and power consumption that is an order of magnitude lower compared to prior solutions. A second prototype in 22-nm FD-SOI CMOS demonstrated a beamforming receiver based on the resampling TTDs that can be reconfigured between analog and digital beamforming modes. This reconfigurability is achieved by integrating an ADC with the TTD. The second prototype achieved beamforming for a 2 GHz instantaneous bandwidth reaching 100 % fractional bandwidth at the low end of the 1--6 GHz frequency range. The second prototype was also used to demonstrate TTD beam-nulling which enables a frequency-independent notch direction for improved in-band spatial filtering. The implementations demonstrate the benefits of the resampling true-time-delays.
  • Wideband Time-Based Data Converters
    (2022) Järvinen, Okko
     School of Electrical Engineering | Doctoral dissertation (article-based)
    Rapid development of integrated circuit (IC) technologies has enabled the emergence of powerful and energy-efficient electronic systems such as smart phones. Nowadays, such devices can process immense amounts of data, which places stringent requirements on wireless data transmission and reception. The new fifth generation (5G) standard supports wide bandwidths and high data rates, which necessitates high-speed analog-to-digital converters (ADCs). The ongoing CMOS process scaling continues to improve the performance of digital circuits, while posing additional challenges for the circuit structures used for the necessary analog functions. Hence, digital-intensive ADC solutions are needed to realize high-performance ADCs in modern CMOS processes. One such design approach is time-based ADCs, where analog information is mapped to the time intervals of a digital signal, and is processed by mostly digital circuit structures.  This work explores techniques related to time-based and digital-intensive analog-to-digital (A/D) conversion in terms of voltage-to-time (V/T) and time-to-digital (T/D) conversion. One of the central outcomes of the research is the use of a cyclic-coupled ring oscillator (CCRO) to achievesub-gate-delay time resolution in a time-to-digital converter (TDC). Two prototype ICs are implemented in a 28-nm CMOS process to demonstrate the circuit concepts developed in this work. The first prototype IC demonstrates a 100--750-MS/s CCRO-TDC, which achieves a peak linear resolution of 9.29 bits and a sub-gate-delay time resolution of 4.4 ps. The results verify the robust delay interpolation provided by the CCRO, and highlight the potential of CCROs in time-domain converter applications. The second prototype IC demonstrates the application of time-interleaving (TI) to the time-based converter. The IC contains a time-based TI-ADC with 2-GS/s sample rate and 40-dB SNDR, as well as a 1.5-GS/s TI-TDC with a 10.1-bit linear resolution at 2.3-ps time resolution. The implemented designs demonstrate the effectiveness of the developed time-based circuit concepts in the context of wideband time-based ADCs.