Browsing by Author "Stadius, Kari, Dr., Aalto University, Finland"

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    Integrated RF Transmitter Front-End for Frequency Reconfigurable Antenna Clusters
    (Aalto University, 2022) Saleem, Ali Raza; Stadius, Kari, Dr., Aalto University, Finland; Elektroniikan ja nanotekniikan laitos; Department of Electronics and Nanoengineering; Sähkötekniikan korkeakoulu; School of Electrical Engineering; Ryynänen, Jussi, Prof., Aalto University, Department of Electronics and Nanoengineering, Finland
    During recent years, the next generation integrated RF transceivers have continuously come up with stringent user demands and related arduous design challenges. The major requirements of wideband spectrum coverage and higher data rates have been achieved with frequency agile multiantenna systems. However, the system complexity that has resulted from such systems has created challenges for the interfacing hardware community: RF integrated circuit (IC) design in search of compact and efficient on-chip solutions needed to drive multiantenna systems. This dissertation presents advances related to an RF transmitter front-end for the sub-6 GHz and Ka-band, with special focus on the driving and tuning of frequency reconfigurable antenna clusters. Specifically, this work addresses the antenna cluster tuning concept from the implementation perspective, and provides an integrated transmitter front-end design which can tune the antenna cluster frequency response with only weighted signal generation. This unique concept developed at Aalto University, eliminates the required on-chip/off-chip matching components residing at the transmitter and antenna interface. The research work is demonstrated with one transmitter IC implementation and five peer-reviewed scientific publications. In the context of integrated transmitter front-end design, this thesis focuses on the replacement of typical tuning solutions based on discrete electronics for frequency-agile antenna. The antenna prototypes used in this work have been provided by the Radio group at Aalto University, Finland. The transmitter IC fabricated in a 28-nm CMOS technology, provides a robust on-chip weighted signal generation for two antenna prototypes: Firstly, the prototype demonstration in an anechoic chamber has validated the antenna tuning concept with a four-monopole cluster driven with the transmitter IC. This prototype provides antenna cluster tuning of across a wideband from 1. 5 GHz to 5 GHz without using any tuning components. Afterwards, the experimental verification was extended to investigate a modulated signal transmission feature. Also, the design optimization case study is presented from a scaling perspective which also addresses the challenges at the TX and antenna interface. Finally, the same transmitter IC verified the operation of another antenna cluster prototype consisting of 8 elements operating as an MIMO for the first time from the 0.5 GHz to 4.5 GHz spectrum along with an envelope correlation coefficient residing below 0.4. The second transmitter front-end study has been conducted for Ka-band (26.5 GHz- 40 GHz applications where the switched-mode power amplifier topology named switched-capacitor power amplifier topology operation is analyzed and studied for the first time. In particular, the operation at 30 GHz reveals that the simulation with foundry device models can provide an output power of 18.6 dBm with a drain efficiency of 20%, and the OFDM-modulated signals of bandwidth 100 MHz and 400 MHz result into adjacent channel leakage ratio of -34.4 dB and -32.8 dB respectively.  
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    Multi-output Synthesizers for Integrated Transceivers
    (Aalto University, 2022) Antonov, Yury; Stadius, Kari, Dr., Aalto University, Finland; Elektroniikan ja nanotekniikan laitos; Department of Electronics and Nanoengineering; Sähkötekniikan korkeakoulu; School of Electrical Engineering; Ryynänen, Jussi, Prof., Aalto University, Department of Electronics and Nanoengineering, Finland
    This thesis focuses on concepts, designs and implementations of various multi-output clocking circuits for RF front-ends in mobile terminals. A total of three experimental concepts and five evaluation designs are discussed. Two in-situ calibration concepts are shown to equalize the latencies between plural outputs in stretched multi-output arrangements. Both calibration techniques demonstrated that a digital engine can be run directly from multiple outputs while calibrating their latencies and locking the chained stages delay to the reference cycle. A third side concept of over-an-octave frequency source is presented in the form of a switched-oscillator stacked within a distributed multiplexing network for which the simulations supported the frequency coverage of the stacked oscillators. Two evaluation designs of multi-output code-to-time converters are presented in distinct implementations that eliminate the bulky arrays of passive components. The first embodiment uses active delay cells in branched chains to generate driving waveforms for a quadratures mixer in the receiver and demonstrates LO-phase shifting sufficient for practical beamsteering applications. The second all-digital embodiment with a theoretically unbounded number of delaying channels and a shared communication bus demonstrates a delay tuning range wide enough for sub-6GHz phase modulators. The third prototype design in this work is an all-digital inductor-less PLL driving the frequency multiplier. It is shown by the presented implementation that a PLL-controled ring oscillator can generate multiple phase shifted signals for the inputs of the frequency multiplier. The discussed arrangement exploits a small area and the wide tunability benefits of a sub-6GHz ring oscillator and uses programmable multiplication to translate PLL output frequency into several Gb/s data-rates, thus reducing exclusive pins for an application processor in the limited mobile space. The fourth evaluation design discussed in the thesis is delay-line based multiplier for fractional-N multiplication of the reference frequency. It is verified in the presented work that large frequency jumps can be achieved without compromising the resolution of the channel selection, which makes it possible to rapidly search for unoccupied spectrum in sub-6GHz front-ends. Furthermore, the output quantization noise after frequency multiplication can be shaped with a delta-sigma modulator and output deterministic jitter can be significantly reduced with a post-modulator. The fifth implementation presented in this work is a synthesizer of the pulse streams for multiple mixers in paralleled receiving front-ends. The thesis demonstrates that the generation of pulses can be split into waveform generation and further processing of the waveform, which supports on-chip scalability both in the number of driven mixers and output phases. Furthermore, since pulses are separately generated  close to mixers, there is no need for a synthesizer-centered layout.