Browsing by Author "Stadius, Kari, Dr., Aalto University, Department of Electronics and Nanoengineering, Finland"

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    Digital-Intensive Transmitters and Power Amplifiers for Integrated Radio Systems
    (Aalto University, 2019) Martelius, Mikko; Stadius, Kari, Dr., Aalto University, Department of Electronics and Nanoengineering, Finland; Elektroniikan ja nanotekniikan laitos; Department of Electronics and Nanoengineering; Sähkötekniikan korkeakoulu; School of Electrical Engineering; Ryynänen, Jussi, Prof., Aalto University, Department of Electronics and Nanoengineering, Finland
    This dissertation presents research advancing theoretical and practical knowledge on digital-intensive integrated sub-6-GHz radio transmitters with special focus on power amplifiers (PAs). New radio standards and CMOS process scaling create demand for innovative solutions to push the digital-to-analog boundary closer to the antenna, while the goal of maximizing efficiency calls for transmitter architectures that enable using nonlinear switch-mode power amplifiers. This work explores the possibilities and limitations of integrated multilevel outphasing transmitters in this context, and develops new techniques to overcome shortcomings that were observed. These objectives are pursued with methods ranging from analysis and simulations to design, implementation and characterization of prototype circuits. The original research consists of three parts, the first of which focuses on system-level development of digital-intensive transmitters. This includes analysis of spectral degradation caused by discrete-time amplitude levels in polar and multilevel outphasing transmitters, which is shown to be canceled by a voltage-subtracting power combiner. In addition, it is demonstrated that discontinuities in harmonic content can limit the spectral performance of multilevel outphasing transmitters, and a new transmitter architecture called tri-phasing is proposed to eliminate the problem. Two integrated transmitter implementations in 28-nm CMOS are presented, one of which uses multilevel outphasing, while the other verifies the functionality of tri-phasing. The second part describes analysis and design of multilevel CMOS PAs intended for highly integrated transmitters. A cascoded class-D output stage complicates the task of switching PA units on and off during transmission, which is required by multilevel operation. This is solved with on/off logic that constructs the desired signal after biasing circuitry. This section presents the design of two eight-unit class-D PAs in 28-nm CMOS utilizing variations of the on/off logic. One of the PAs was implemented on the same die with other parts of the tri-phasing transmitter, constituting the highest achieved level of integration among multilevel outphasing-based transmitters. The final part of this work examines power combining with transmission-line-based circuits implemented on printed circuit boards. The presented analysis demonstrates that the choice of power-combiner type can be critical for suppressing detrimental voltage ripple at the supply and ground of a wire-bonded PA circuit. Two power combiners were designed for the presented PAs, the first of which uses a voltage-adding structure based on quarter-wave transmission lines. The second combiner design relies on the extended Marchand balun, a new coupled-line structure for voltage-subtracting combiners, which introduces an additional degree of freedom by including arbitrarily long input lines. The latter combiner was measured as part of the tri-phasing transmitter.
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    Integrated Radio-Frequency Receivers for RF-to-Digital Converters
    (Aalto University, 2019) Ul Haq, Faizan; Stadius, Kari, Dr., Aalto University, Department of Electronics and Nanoengineering, Finland; Elektroniikan ja nanotekniikan laitos; Department of Electronics and Nanoengineering; Sähkötekniikan korkeakoulu; School of Electrical Engineering; Ryynänen, Jussi, Prof., Aalto University, Department of Electronics and Nanoengineering, Finland
    The widespread usage of mobile communication in recent decades has crowded the frequency spectrum with multiple bands and communication standards. An ideal wireless receiver for such a scenario will need to cover all frequency bands/standards with the possibility of instant reconfigurability through software control. The receiver should also be entirely integrated to gain the advantages of mobility and cheaper production costs. The ultimate goal of an ideal receiver is encapsulated in the concept of software-defined radio (SDR). An attractive approach to realize an SDR is an RF-to-digital converter. In best case, an RF-to-digital converter consists of an analog-to-digital converter (ADC) which is directly connected to a wideband antenna. This means that the received signal on the antenna is immediately converted in the digital domain where reconfigurability is easy to achieve. However, such a complete RF-to-digital converter has so far proved to be an elusive goal due to impractically high power consumption requirements of ADC in the GHz range. Therefore, a practical RF-to-digital converter is followed by an RF front-end which reduces the power consumption requirements of an ADC by signal amplification, filtering, and frequency down-conversion. SDR research for such a practical case is focused towards reconfigurable, wideband and digital intensive RF front-ends. It is also targetted at reducing the number of parallel receiver front-ends by implementing a single wideband and fully integrated front-end capable of receiving all frequency bands/standards. To design receiver solutions for such a practical RF-to-digital converter, new techniques are needed to overcome the design challenges. This thesis focuses on finding new solutions to four of these design challenges related to the goal of RF-to-digital converters: 1) Blocker tolerance in wideband RF front-ends; 2) harmonic rejection RF-front ends with on-chip N-path filtering; 3) transmitter self leakage cancellation, and; 4) blocker rejection and sensitivity issues in direct delta sigma receivers. Starting from the detailed description of these challenges, research outcomes on both theoretical and experimental fronts are presented. In particular, a harmonic-rejection receiver was fabricated in 28nm fully-depleted silicon-on-insulator (FDSOI) technology. The receiver attempts to resolve many of the above-mentioned challenges through higher-order on-chip filtering, simple local-oscillator clocking, and a two-stage harmonic-rejection implementation. The receiver front-end also includes a novel transmitter signal-leakage cancellation technique through buried-gate signaling in an FDSOI process. In addition to the fabricated receiver, the thesis incorporates two new blocker attenuation techniques at the input of the low-noise amplifier in the receiver chain. On the theoretical front, sensitivity issues in direct delta sigma receivers are analyzed with detailed theoretical modeling leading to simple design guidelines. Details of all these contributions can be found in the author's publications I-IX.