Browsing by Author "Stadius, Kari"
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Item A 0.35-to-2.6GHz multilevel outphasing transmitter with a digital interpolating phase modulator enabling up to 400MHz instantaneous bandwidth(2017-03-02) Kosunen, Marko; Lemberg, Jerry; Martelius, Mikko; Roverato, Enrico; Nieminen, Tero; Englund, Mikko; Stadius, Kari; Anttila, Lauri; Pallonen, Jorma; Valkama, Mikko; Ryynänen, Jussi; Department of Electronics and Nanoengineering; Department of Micro and Nanosciences; Jussi Ryynänen Group; Nokia; Tampere University of TechnologyAdvanced wireless radio standards set stringent requirements on the bandwidth, frequency range and reconfigurability of base-station transmitters. Recently, the outphasing concept has shown promise of wide bandwidth while taking advantage of process scaling with extensive exploitation of rail-to-rail signaling. Recent outphasing transmitter designs have often focused on power-amplifier (PA) and power-combiner implementations while omitting the phase modulator [1,2]. Moreover, previously reported transmitters with integrated digital phase modulators have only shown bandwidths up to 40MHz [3,4], although 133MHz has been demonstrated at 10GHz carrier frequency utilizing phase modulators based on conventional IQ-DACs [5]. Thus, digital-intensive outphasing transmitters capable of modulation with hundreds of MHz bandwidth at existing cellular frequency bands have not yet been published. To address the aforementioned challenge, this paper introduces a multilevel outphasing transmitter with four amplitude levels, including the first prototype implementation based on the digital interpolating phase modulator concept [6]. The transmitter is targeted for 5G picocell base stations and has been verified to operate with instantaneous bandwidth up to 400MHz. In addition, the developed phase modulator eliminates the need for complex on-chip frequency synthesizers by introducing digital carrier frequency generation, demonstrated between 0.35 and 2.6GHz, while utilizing a single 1.8GHz reference clock.Item A 0.6–4.0 GHz RF-Resampling Beamforming Receiver with Frequency-Scaling True-Time-Delays up to Three Carrier Cycles(IEEE, 2020) Spoof, Kalle; Zahra, Mahwish; Unnikrishnan, Vishnu; Stadius, Kari; Kosunen, Marko; Ryynänen, Jussi; Department of Electronics and Nanoengineering; Jussi Ryynänen GroupTrue-time-delays (TTDs) enable wideband analog and hybrid beamforming by mitigating the beam squint problem. This letter reports a TTD beamforming receiver supporting delays up to three carrier-frequency cycles. The implementation is the first published work in which the delays scale with the carrier frequency. The scaling enables TTDs for large arrays at low-GHz frequencies where long delays are required due to \lambda _{c}/2 antenna spacing. The delays are implemented through delayed resampling of a passive mixer's discrete-time output. Driving the mixers with pulse-skipped local oscillator (LO) signals allows the delay range to exceed one carrier cycle. A polyphase receiver structure prevents aliasing of noise and unwanted tones caused by LO pulse-skipping. Our prototype implementation demonstrates squint-free beamforming for an-800 MHz instantaneous RF bandwidth. The proposed TTD is efficient for large arrays since the power consumption per antenna is only 5-13-mW across the 0.6-4.0-GHz frequency range. The prototype was implemented in 28-nm FD-SOI CMOS, and the die area including bonding pads is only 1.2 mm2.Item A 0.9-Nyquist-Band Digital Timing Mismatch Correction for Time-Interleaved ADCs Achieving Delay Tuning Range of 0.12-Sample-Period(2022) Kempi, Ilia; Jarvinen, Okko; Kosunen, Marko; Unnikrishnan, Vishnu; Stadius, Kari; Ryynanen, Jussi; Department of Electronics and Nanoengineering; Jussi Ryynänen GroupTime-interleaved analog-to-digital converters (TIADC) require channel matching in terms of offset, gain, and sampling clock skew to achieve best data conversion performance. Conventionally, correction of skew mismatch is realized with analog delay lines, making it challenging for high-speed ADC designs to achieve fine delay resolution over wide tuning range while maintaining low clock jitter. Digital skew correction allows greater flexibility than analog solutions, but is hindered by a significant hardware footprint. This paper demonstrates digital filter-based timing skew correction approach suitable for on-chip implementation. In a 10-bit 8-channel TI-ADC the proposed structure corrects mismatch magnitudes up to 0.12 sample period across 0.9 Nyquist band while requiring only 65% hardware of similar architectures of equivalent performance. The presented digital circuit uses reduced combinational paths and operates at a clock rate of single ADC channel, making it applicable for digitally-assisted high-speed TI-ADCs.Item A 1.5-1.9-GHz all-digital tri-phasing transmitter with an integrated multilevel class-D power amplifier achieving 100-MHz RF bandwidth(Institute of Electrical and Electronics Engineers, 2019-06-01) Lemberg, Jerry; Martelius, Mikko; Roverato, Enrico; Antonov, Yury; Nieminen, Tero; Stadius, Kari; Anttila, Lauri; Valkama, Mikko; Kosunen, Marko; Ryynänen, Jussi; Department of Electronics and Nanoengineering; Jussi Ryynänen Group; Tampere UniversityWe present a prototype RF transmitter with an integrated multilevel class-D power amplifier (PA), implemented in 28-nm CMOS. The transmitter utilizes tri-phasing modulation, which combines three constant-envelope phase-modulated signals with coarse amplitude modulation in the PA. This new architecture achieves the back-off efficiency of multilevel outphasing, without linearity-degrading discontinuities in the RF output waveform. Because all signal processing is performed in the time domain up to the PA, the entire system is implemented with digital circuits and structures, thus also enabling the use of synthesis and place-and-route CAD tools for the RF front end. The effectiveness of the digital tri-phasing concept is supported by extensive measurement results. Improved wideband performance is validated through the transmission of orthogonal frequency-division multiplexing (OFDM) bandwidths up to 100 MHz. Enhanced reconfigurability is demonstrated with non-contiguous carrier aggregation and digital carrier generation between 1.5 and 1.9 GHz without a frequency synthesizer. For a 20-MHz 256-QAM OFDM signal at 3.5% error vector magnitude (EVM), the transmitter achieves 22.6-dBm output power and 14.6% PA efficiency. Thanks to the high linearity enabled by tri-phasing, no digital predistortion is needed for the PA.Item A 1.5-5-GHz Integrated RF Transmitter Front End for Active Matching of an Antenna Cluster(IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2020-11) Saleem, Ali; Stadius, Kari; Hannula, Jari-Matti; Lehtovuori, Anu; Kosunen, Marko; Viikari, Ville; Ryynänen, Jussi; Department of Electronics and Nanoengineering; Jussi Ryynänen Group; Ville Viikari GroupA recently proposed method for realizing frequency-reconfigurable antennas across a wideband is based on adjusting the feed amplitudes and phases of a multiport antenna. In this article, we demonstrate the feasibility of the method, for the first time, with a conjunction of an integrated RF transmitter and a four-element antenna cluster. The implementation performs on-chip amplitude and phase tuning with supply scaling and delay tuning circuits to tune the antenna cluster without requirement of matching network. The antenna cluster is built with four closely spaced antenna elements implemented on a printed circuit board. The transmitter integrated circuit (IC) is implemented in a 28-nm CMOS process with the chip size of 0.85 mm x 0.95 mm, including pads. The proof-of-concept implementation demonstrates tunability across a wideband from 1.5 to 5 GHz.Item A 100–750 MS/s 11-Bit Time-to-Digital Converter With Cyclic-Coupled Ring Oscillator(IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2021-03-24) Jarvinen, Okko; Unnikrishnan, Vishnu; Siddiqui, Waqas; Korhonen, Teuvo; Koli, Kimmo; Stadius, Kari; Kosunen, Marko; Ryynanen, Jussi; Department of Electronics and Nanoengineering; Jussi Ryynänen Group; Department of Electronics and Nanoengineering; Huawei TechnologiesThis paper presents the first measured cyclic-coupled ring oscillator (CCRO) time-to-digital converter (TDC). The CCRO realizes a robust true time-domain delay interpolation with sub-gate-delay resolution. The architecture employs real-time quantization to reduce conversion time and hence maximize bandwidth. Furthermore, the CCRO phase progression is encoded with a bubble error suppression logic, thereby building resilience to delay mismatches from circuit/layout imperfections. The prototype circuit implemented in a 28 nm CMOS process demonstrates a combination of high resolution and high sample rate over wide range of sample rates. The TDC achieves its peak figure-of-merit (FoM) of 0.051 pJ/conv.-step at 100 MS/s while delivering 8.38-bit linear resolution and 15.4 ps time resolution, operating from a 0.55 V supply. The TDC demonstrates the highest reported linear resolution of 9.29 bits among converters operating above 100 MS/s, at 125 MS/s and 0.9 V supply, while achieving 4.4 ps time resolution and 0.16 pJ/conv.-step FoM. Further, the real-time quantizing architecture allows fast operation up to 750 MS/s, where the TDC delivers 6-bit linear resolution and 0.48 pJ/conv.-step FoM operating from 0.9 V supply.Item An 18–28 GHz dual-mode down-converter IC for 5G applications(Springer, 2024-02) Naghavi, Saeed; Ryynänen, Kaisa; Zahra, Mahwish; Korsman, Aleksi; Stadius, Kari; Kosunen, Marko; Unnikrishnan, Vishnu; Anttila, Lauri; Valkama, Mikko; Ryynänen, Jussi; Department of Electronics and Nanoengineering; Jussi Ryynänen Group; Department of Electronics and Nanoengineering; Tampere UniversityEmerging spectrum trends require a higher integration of 5G New Radio Frequency Range 1 (FR1) and Frequency Range 2 (FR2) bands to enhance the availability of spectrum and spectrum-sharing opportunities. To enable the reception of both FR1 and FR2 bands in a seamless hardware entity, we propose combining homodyne and heterodyne architectures. This necessitates the incorporation of a down-converter module that transfers the incoming signals from FR2 bands down to FR1, ensuring compatibility with an FR1 direct-conversion receiver (DCR) for the final signal reception. The primary focus of this paper is the design and implementation of the required integrated down-converter. The module includes an integrated balun, a low-noise amplifier (LNA) with a bypass mode, a dual-mode mixer, and an intermediate frequency (IF) amplifier. The introduced bypass mode helps to further elevate the linearity performance compared to the nominal mode. The bypass mode is designed for joint communication and sensing operation to avoid the compression of the receiver. This work also incorporates a local oscillator (LO) signal distribution network with phase tuning elements using a mixed-signal approach. The circuit is implemented in a 22-nm CMOS process, and the active die area is 0.6 mm 2 . The measurements demonstrate that the implemented chip can efficiently perform the required frequency conversion over a wide frequency range of 18–28 GHz. Conversion gain of 4.5–7.5 dB, noise figure of 15–19.7 dB, 1 dB compression point (IP1dB) of − 16 to − 10 dBm, and input third-order intercept point (IIP3) of − 5 to 0 dBm are achieved. The measured IP1 dB and IIP3 for the bypass mode are +0.5 to +4.5 dBm and +8.5 to +10 dBm, respectively.Item A 2 GS/s 9-bit Time-Interleaved SAR ADC with Overlapping Conversion Steps(2022) Tenhunen, Miikka; Spoof, Kalle; Unnikrishnan, Vishnu; Stadius, Kari; Kosunen, Marko; Ryynanen, Jussi; Department of Electronics and Nanoengineering; Jussi Ryynänen Group; Department of Electronics and Nanoengineering; Tampere UniversityThis paper presents a wideband 8-way time-interleaved (TI) 9-bit successive approximation register (SAR) analog-to-digital converter (ADC) with overlapping conversion steps that improve the speed of operation. The ADC generates its clocks using a synchronous counter based circuit which reduces the SAR delay. A common-mode reference based split capacitor array digital-to-analog converter (DAC) is implemented that achieves high speed and low power consumption. Simulation results are presented for the ADC designed in a 22 nm CMOS process. The TI ADC achieves at least 7.7 ENOB at 2 GS/s and consumes a total of 19.8 mW from 0.8 V supplies, resulting in 47.6 fF/conv-step. The single ADC achieves 8.34 ENOB at 250 MS/s, consuming 1.43 mW in total and 17.7 fF/conv-step.Item A 2-5.5 GHz Beamsteering Receiver IC With 4-Element Vivaldi Antenna Array(IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2020-09) Zahra, Mahwish; Kempi, Ilia; Haarla, Jaakko; Antonov, Yury; Khonsari, Zahra; Miilunpalo, Toni; Ahmed, Nouman; Inkinen, Juha; Unnikrishnan, Vishnu; Lehtovuori, Anu; Viikari, Ville; Anttila, Lauri; Valkama, Mikko; Kosunen, Marko; Stadius, Kari; Ryynänen, Jussi; Department of Electronics and Nanoengineering; Jussi Ryynänen Group; Ville Viikari Group; Jussi Ryynänen Group; Tampere UniversityIn this article, we present a four-element Vivaldi antenna array and beamsteering receiver IC for the fifth-generation mobile network (5G) new radio (NR). The implemented receiver utilizes a delay-based local-oscillator phase shift technique for accurate beamsteering, and it exhibits 1° to 2.4° phase tuning capability for 2-5 GHz bandwidth accordingly. On-chip delay measurement is performed with pilot signal generation and delay estimation capable of 2-ps accuracy. The IC is fabricated on 28-nm CMOS technology, it occupies an area of 1.4x1.4 mm^2, including bonding pads, and consumes 22.8 mW at 2 GHz for single-receiver path operation. The receiver demonstrates wideband over-the-air reception with the prototype antennas.Item A 20-60GHz Digitally Controlled Composite Oscillator for 5G(2018) Antonov, Yury; Tormanen, Markus; Ryynänen, Jussi; Pärssinen, Aarno; Stadius, Kari; Department of Electronics and Nanoengineering; Jussi Ryynänen Group; Lund University; University of OuluThis paper describes a frequency generator supporting over-an-octave tuning range for 5G receiver front-end. Generator is built by composition of smaller-range oscillators multiplexed to the common output that drives a downconversion mixer. Simulated in 28nm CMOS with full physical device models the composite oscillator exhibits a frequency tuning range from 21.5 to 60.7GHz (95.3%) dissipating less then 25.8mW from a 0.9V supply. As a result, it achieves −184dBc/Hz FOM TR.Item A 3-43ps time-delay cell for LO phase-shifting in 1.5-6.5GHz beamsteering receiver(2018) Antonov, Yury; Zahra, Mahwish; Stadius, Kari; Khonsari, Zahra; Ahmed, Nouman; Kempi, Ilia; Inkinen, Juha; Unnikrishnan, Vishnu; Ryynänen, Jussi; Department of Electronics and Nanoengineering; Jussi Ryynänen GroupThis paper describes a digital-friendly passives-less time delay cell that generates programmable phase-shifts for down converting front-end in LO-based beamsteering receiver. Cell design supports 1.5–6.5GHz broadband receiver operation and cell layout occupies an area of only 15×16.5μm 2 including power supply rails and control logic. Simulated in 28nm CMOS technology, delay cell exhibits 6 distinct delay values {3, 3.5, 17, 19, 24, 43}ps consuming at most 220μW@IV.Item A 30-dBm class-D power amplifier with on/off logic for an integrated tri-phasing transmitter in 28-nm CMOS(2018-08-07) Martelius, Mikko; Stadius, Kari; Lemberg, Jerry; Roverato, Enrico; Nieminen, Tero; Antonov, Yury; Anttila, Lauri; Valkama, Mikko; Kosunen, Marko; Ryynanen, Jussi; Department of Electronics and Nanoengineering; Jussi Ryynänen Group; Tampere University of Technology; CoreHW OyThis paper presents an eight-unit class-D power amplifier (PA), implemented in 28-nm CMOS. The PA is designed to utilize tri-phasing modulation, which combines coarse-amplitude polar modulation with fine-resolution outphasing components. This new technique enables achieving the back-off efficiency of multilevel outphasing without linearity-degrading discontinuities in the output waveform. Each PA unit contains a cascoded output stage with a 3.6-V supply voltage, and on/off logic enabling multilevel operation controlled by low-voltage signals. The PA achieves a peak output power of 29.7 dBm with a 34.7% efficiency, and is verified to operate with aggregated LTE signals at bandwidths up to 60 MHz at 1.7-GHz carrier frequency.Item A 30-GHz Switched-Capacitor Power Amplifier for 5G SoCs(2020-11-23) Saleem, Ali Raza; Stadius, Kari; Kosunen, Marko; Anttila, Lauri; Valkama, Mikko; Ryynanen, Jussi; Department of Electronics and Nanoengineering; Jussi Ryynänen Group; Tampere UniversitySwitched-capacitor power amplifier has gained popularity within the radio frequency integrated circuit community, since it is CMOS compatible offering high integration density and good performance particularly in terms of linearity. In this paper we present a study on the use of switched-capacitor power amplifier at millimeter-wave frequency range. We identify the major design challenges in this paper, and demonstrate the feasibility of switched-capacitor power amplifier with a 30-G Hz design case. Our analysis describes the effects of power amplifier device parasitics and their contribution to dynamic power consumption, revealing that these are a major factor in degradation of switched capacitor power amplifier efficiency at millimeter waves. Two circuits, one for 3 GHz and the other for 30 GHz, were designed and simulated with 28-nm bulk CMOS technology. At 3 GHz, the designed switched capacitor power amplifier structure with 6-bit resolution features maximum output power of 19.4 dBm and efficiency of 59% whereas the output power of 18.6 dBm with 21% efficiency is achieved at 30 GHz. The switched-capacitor power amplifier preserves its good linearity at higher frequencies as well, and our design demonstrates an adjacent channel leackage ratio of -34.4 dB at 30 GHz for a 100-MHz OFDM-modulated signal.Item A 38.5-to-60.5 GHz LNA with Wideband Combiner Supporting Cartesian Beamforming Architecture(2021-09-13) Akbar, Rehman; Shaheen, Rana A.; Rahkonen, Timo; Tze, Cheung; Stadius, Kari; Parssinen, Aarno; Department of Electronics and Nanoengineering; Jussi Ryynänen Group; University of OuluCurrent millimetre-wave (mmW) 5G NR standard supports multiple bands at 24.5/28/37/39/43/47GHz for communications. To cover several bands of the 5G NR and reaching lower end of unlicensed 60GHz band for 802.11ad, this work presents a wideband phased array front-end with LNA and two VGAs for scalar-only weighting function, and a wideband combining network of each signal weight in mmW domain for beamforming. In this work, two array elements are combined in two cascaded stages for extremely wideband operation. Combined load resonances are distributed and adjusted appropriately in each of the combining stages to achieve a flat response over the band of 38.5-60.5GHz. A single array path achieves rms gain of 8.5-12.5dB, noise figure of 6.2-8.1dB, and IP1dB of -33 to - 26dBm. The measurements show ≈ 6dB of array gain when the two phased array elements are combined in phase with +0.6dB to -0.4dB maximum gain error in the mmW VGAs. The prototype is implemented using 28nm CMOS.Item A 5.4-GHz 2/3/4-modulus fractional frequency divider circuit in 28-nm CMOS(2021) Cheung, Tze Hin; Ryynänen, Jussi; Pärssinen, Aarno; Stadius, Kari; Department of Electronics and Nanoengineering; Jussi Ryynänen Group; University of OuluThis paper describes the design and post-layout simulations of a 2/3/4- modulus frequency divider circuit, accompanied with an accumulator that controls the division count. The circuit is capable of operating as an integer or as a fractional divider. Key topic of this paper is the merging of div-2/3 and div-3/4 circuits into a single compact circuit that solves an issue of a forbidden state in fractional-division operation. The circuit is designed with 28-nm CMOS technology and the post-layout simulations indicate an operating input frequency range of 0.3 - 5.4 GHz with 13-bit fractional frequency resolution between division ratios of 2-4. The divider occupies only 40 µm x 30 µm while consuming 2.0 mW at 5.4 GHz input frequency.Item 55-100-GHz Enhanced Gilbert Cell Mixer Design in 22-nm FDSOI CMOS(IEEE, 2024) Jokiniemi, Kimi; Ryynanen, Kaisa; Vaha, Joni; Kankkunen, Elmo; Stadius, Kari; Ryynanen, Jussi; Department of Electronics and Nanoengineering; Jussi Ryynänen Group; Marko Kosunen Group; Department of Electronics and Nanoengineering; Jussi Ryynänen GroupThis article presents a wideband active millimeter wave (mmWave) CMOS downconversion mixer preceded by thorough analysis. This article aims to provide solid reasoning for the proper choice of mixer topology and present methods to achieve high mixer performance, guiding mmWave mixer design. The article first analyses passive and active mixer input impedance and switching performance with a weak sinusoidal local oscillator (LO) signal, demonstrating that passive mixer switching performance is far more dependent on the LO signal. The article then introduces different active mixer design enhancement techniques, namely, peaking inductances and individual mixer stage biasing. The article proposes an enhanced Gilbert cell mixer that uses transformer coupling between the transconductance and switching stages. The complete mixer structure with an LO buffer and an IF amplifier consumes an area of only 0.13 mm2 fabricated in a 22-nm FDSOI process. The design achieves a measured peak voltage conversion gain (CG) of 3.5 dB, an exceptionally wide 55-100-GHz RF bandwidth, and a 10-GHz IF bandwidth. The complete mixer consumes 33 mW of power from a low 0.8-V supply voltage and demonstrates an input 1-dB gain compression point of -6 dBm.Item A 6–20 GHz 400-MHz Modulation-Bandwidth CMOS Transmitter IC(2022-10-26) Saleem, Ali Raza; Naghavi, Saeed; Zahra, Mahwish; Stadius, Kari; Kosunen, Marko; Anttila, Lauri; Valkama, Mikko; Ryynänen, Jussi; Department of Electronics and Nanoengineering; Jussi Ryynänen Group; Tampere UniversityThis paper presents a transmitter IC with two identical signal paths, including base-band amplifier, up-converting mixer, and power amplifier (PA) stages. The design is focused on wide modulation bandwidth, and the use of a resonatorless small die-area class-D power amplifier at cm-wave frequencies. This work also incorporates a local oscillator (LO) signal distribution network with phase tuning elements. The circuit is implemented in a 22-nm CMOS process, and the active die area is 0.8 mm2. Operation over the 6–20 GHz range of carrier frequencies through the transmission of both continuous wave (CW) and wideband quadrature phase shift keying (QPSK) modulated signals were verified with measurements. Results with 20/40/100, and 400 MHz modulation bandwidths are presented, and for instance for a 20-MHz QPSK modulated input signal the measured adjacent channel leakage ratio (ACLR) of the transmitter is 28 dBc and error vector magnitude (EVM) is 5%.Item Active Wideband 55-100-GHz Downconversion Mixer in 22-nm FDSOI CMOS(2023) Jokiniemi, Kimi; Ryynänen, Kaisa; Vähä, Joni; Kankkunen, Elmo; Stadius, Kari; Ryynänen, Jussi; Department of Electronics and Nanoengineering; Nurmi, Jari; Ellervee, Peeter; Koch, Peter; Moradi, Farshad; Shen, Ming; Jussi Ryynänen Group; Department of Electronics and Nanoengineering; Jussi Ryynänen GroupThis paper presents a wideband active CMOS downconversion mixer for emerging mmWave communication and sensing applications. The designed mixer utilizes transformer coupling between the transconductance stage and switching stage of a classic Gilbert cell mixer to introduce inductive peaking and decouple the stages at DC. This technique efficiently allows the improvement of Gilbert cell mixer bandwidth, gain and linearity. Additionally, the designed mixer structure comprises a transformer-loaded common-source LO buffer and a two-stage wide bandwidth IF amplifier. The complete mixer consumes 33 mW of power from a low 0.8-V supply voltage. The mixer has been implemented with a 22-nm FDSOI CMOS process and its layout area is 0.13 mm 2 . The design achieves a measured peak voltage conversion gain of 3.5 dB and particularly a wide 3-dB RF bandwidth from 55 to 100 GHz, covering a range of mmWave bands with a single device. The mixer also demonstrates a wide 10-GHz IF output bandwidth suitable for high channel bandwidth applications, as well as an input 1-dB gain compression point of -6 dBm.Item Adaptive Nonlinear RF Cancellation for Improved Isolation in Simultaneous Transmit-Receive Systems(2018) Kiayani, Adnan; Waheed, Muhammad Zeeshan; Anttila, Lauri; Abdelaziz, Mahmoud; Korpi, Dani; Syrjala, Ville; Kosunen, Marko; Stadius, Kari; Ryynanen, Jussi; Valkama, Mikko; Department of Electronics and Nanoengineering; Jussi Ryynänen Group; Tampere University of TechnologyThis paper proposes an active radio frequency (RF) cancellation solution to suppress the transmitter (TX) passband leakage signal in radio transceivers supporting simultaneous transmission and reception. The proposed technique is based on creating an opposite-phase baseband equivalent replica of the TX leakage signal in the transceiver digital front-end through adaptive nonlinear filtering of the known transmit data, to facilitate highly accurate cancellation under a nonlinear power amplifier (PA). The active RF cancellation is then accomplished by employing an auxiliary TX chain to generate the actual RF cancellation signal, and combining it with the received signal at the receiver (RX) low-noise amplifier (LNA) input. A closed-loop parameter learning approach, based on the decorrelation learning rule, is also developed to efficiently estimate the coefficients of the nonlinear cancellation filter in the presence of a nonlinear PA with memory, finite passive isolation, and a nonlinear LNA. The performance of the proposed cancellation technique is evaluated through comprehensive RF measurements adopting commercial LTE-Advanced transceiver hardware components. The results show that the proposed technique can provide an additional suppression of up to 54 dB for the TX passband leakage signal at the LNA input, even at very high transmit power levels and with wide transmission bandwidths. Such a novel cancellation solution can, therefore, substantially improve the TX-RX isolation, hence reducing the requirements on passive isolation and RF component linearity, as well as increasing the efficiency and flexibility of the RF spectrum use in the emerging 5G radio networks.Item All digital phase-locked loop in 40 nm CMOS(2014-02-10) Antonov, Yury; Stadius, Kari; Tikka, Tero; Sähkötekniikan korkeakoulu; Ryynänen, Jussi
