Browsing by Author "Simola, Otto"

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  • End-to-End Multi-Target Verification Environment for a RISC-V Microprocessor
    (2023) Korsman, Aleksi; Hirvonen, Verneri; Simola, Otto; Tarkka, Antti; Kosunen, Marko; Ryynanen, Jussi
     A4 Artikkeli konferenssijulkaisussa
    In this paper, we present the end-to-end verification environment developed for verifying A-Core, a custom, extensible and configurable RISC-V microprocessor targeted for controlling communication, cryptography, and machine learning hardware accelerators. The developed open source verification environment utilizes a Python-based ASIC-generic system verification framework. In the developed environment, the processor can be verified with self-checking user-written Assembly- or C-programs, providing a seamless from-C-to-hardware verification methodology. With the presented test platform, test programs can be run on various targets: RTL simulation, FPGA, or ASIC, providing one verification environment for all maturity levels of the design. The platform enables end-to-end testing: verification of the functionality of the A-Core ASIC from the programming sequence over a JTAG interface to printouts over UART, providing tests coverage also for real use cases of the hardware. Performance metrics for different sized test programs are provided to enable characterization of the speed of verification.
  • Ohjelmoitavien järjestelmäpiirien käytännön sovellukset
    (2021-05-05) Simola, Otto
     Sähkötekniikan korkeakoulu | Bachelor's thesis
  • Physical implementation of a RISC-V processor
    (2023-03-20) Simola, Otto
     Sähkötekniikan korkeakoulu | Master's thesis
    The open-source instruction set architecture RISC-V has gained attention after its initial launch. This ISA offers a reduced and extensible set of instructions without compromising on any of the features of typical a processor. In 2020 Aalto University started a RISC-V processor project to begin processor research in Aalto University and to be used as the CPU in other projects. During this project, the processor called “A-core” has been developed into a capable core which can drive various peripherals and run Assembly- or C-programs. The objective of this thesis was to design a complete physical implementation for A-core by developing a RISC-V based and automated development platform. By developing the physical implementation, can the processor be verified and validated under the real life physical constraints. Additionally, the physical implementation allows for broader development of software, the usage of the processor as part of teaching and driving other chips. The RISC-V based and automated development environment developed during this work offers the tools to design and research the physical implementation. The environment also provides the tools for verification and validation so that the implementation can be manufactured with minimal deficits. As a result, the produced physical implementation of A-core included all the features added during the design process, such as accelerators, pipelining and minor structural changes, and the design was verified with use of the automated development environment tools. This design was eventually sent out to be manufactured. After arriving from the manufacturer, the design must be validated with measurements, after which it can be stated to be fully functional and can be utilized in future work at Aalto University.
  • Ulkoiset muistit ja muistiväylät RISC-V-prosessoreille
    (2026-06-02) Lehmusto, Pyry
     Sähkötekniikan korkeakoulu | Bachelor's thesis
    RISC-V on suhteellisen uusi ja yksinkertainen avoimen lähdekoodin prosessori käskykanta-arkkitehtuuri. Työn tarkoituksena oli tehdä yleiskattava katsaus ulkoisen muistin toteutuksista RISC-V-prosessorille. Tämä sisältää eri muistiväylien- sekä niiden kanssa yhteensopivien muistien ominaisuuksien selvittämisen kiinnittäen erityishuomiota datalinjojen määrään ja toteutuksilla saavutettavissa oleviin datansiirtonopeuksiin. Katsaus tehtiin kirjallisuuskatsauksena käyttäen pääosin artikkeleita sekä valmistajien tuotetietoja. Kirjallisuuskatsauksen tuloksena saatiin lista eri muistiväyliä ja niille vaihtoehtoisia muisteja. Eri toteutuksille saatiin määritettyä potentiaaliset datansiirtonopeudet. Eniten vaihtoehtoja löytyi selkeästi kuitenkin SPI sekä I2C väylillä. I2C kuitenkin kykenee huomattavasti rajatumpaan datansiirtoon ja sille sopivat muistit ovat huomattavasti pienempiä. Muistivaihtoehdoista EEPROM ja Flash ovat kustannustehokkaimpia, mutta ne ovat huomattavasti muita hitaampia tallentamaan muistille. MRAM voisi olla yksi ratkaisuista, jos muistille tallentamisen nopeudella on merkitystä. Tuloksena saadut luvut nopeuksista ovat hypoteettisia suurimpia arvoja määritetty valmistajien tuotetietojen perusteella, joten todelliset nopeudet ovat todennäköisesti hitaampia. Tämän takia voisi olla kannattavaa tehdä oikeita fyysisiä kokeita käyttäen eri muistiväyliä ja muisteja.