Browsing by Author "Naghavi, Saeed"
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- An 18–28 GHz dual-mode down-converter IC for 5G applications
A1 Alkuperäisartikkeli tieteellisessä aikakauslehdessä(2024-02) Naghavi, Saeed; Ryynänen, Kaisa; Zahra, Mahwish; Korsman, Aleksi; Stadius, Kari; Kosunen, Marko; Unnikrishnan, Vishnu; Anttila, Lauri; Valkama, Mikko; Ryynänen, JussiEmerging spectrum trends require a higher integration of 5G New Radio Frequency Range 1 (FR1) and Frequency Range 2 (FR2) bands to enhance the availability of spectrum and spectrum-sharing opportunities. To enable the reception of both FR1 and FR2 bands in a seamless hardware entity, we propose combining homodyne and heterodyne architectures. This necessitates the incorporation of a down-converter module that transfers the incoming signals from FR2 bands down to FR1, ensuring compatibility with an FR1 direct-conversion receiver (DCR) for the final signal reception. The primary focus of this paper is the design and implementation of the required integrated down-converter. The module includes an integrated balun, a low-noise amplifier (LNA) with a bypass mode, a dual-mode mixer, and an intermediate frequency (IF) amplifier. The introduced bypass mode helps to further elevate the linearity performance compared to the nominal mode. The bypass mode is designed for joint communication and sensing operation to avoid the compression of the receiver. This work also incorporates a local oscillator (LO) signal distribution network with phase tuning elements using a mixed-signal approach. The circuit is implemented in a 22-nm CMOS process, and the active die area is 0.6 mm 2 . The measurements demonstrate that the implemented chip can efficiently perform the required frequency conversion over a wide frequency range of 18–28 GHz. Conversion gain of 4.5–7.5 dB, noise figure of 15–19.7 dB, 1 dB compression point (IP1dB) of − 16 to − 10 dBm, and input third-order intercept point (IIP3) of − 5 to 0 dBm are achieved. The measured IP1 dB and IIP3 for the bypass mode are +0.5 to +4.5 dBm and +8.5 to +10 dBm, respectively. - A 6–20 GHz 400-MHz Modulation-Bandwidth CMOS Transmitter IC
A4 Artikkeli konferenssijulkaisussa(2022-10-26) Saleem, Ali Raza; Naghavi, Saeed; Zahra, Mahwish; Stadius, Kari; Kosunen, Marko; Anttila, Lauri; Valkama, Mikko; Ryynänen, JussiThis paper presents a transmitter IC with two identical signal paths, including base-band amplifier, up-converting mixer, and power amplifier (PA) stages. The design is focused on wide modulation bandwidth, and the use of a resonatorless small die-area class-D power amplifier at cm-wave frequencies. This work also incorporates a local oscillator (LO) signal distribution network with phase tuning elements. The circuit is implemented in a 22-nm CMOS process, and the active die area is 0.8 mm2. Operation over the 6–20 GHz range of carrier frequencies through the transmission of both continuous wave (CW) and wideband quadrature phase shift keying (QPSK) modulated signals were verified with measurements. Results with 20/40/100, and 400 MHz modulation bandwidths are presented, and for instance for a 20-MHz QPSK modulated input signal the measured adjacent channel leakage ratio (ACLR) of the transmitter is 28 dBc and error vector magnitude (EVM) is 5%. - A Compact and Wideband mmWave Passive CMOS Circulator Based on Switched All-Pass Networks
A1 Alkuperäisartikkeli tieteellisessä aikakauslehdessä(2024) Naghavi, Saeed; Gao, Jian; Stadius, Kari; Ryynänen, JussiThis letter presents a compact and wideband passive CMOS circulator for mmWave phased array transceivers. The letter focuses on achieving a compact die area while still offering competitive performance in terms of loss, isolation, and linearity. Our implemented circulator includes two reciprocal phase shift branches as well as a single-path nonreciprocal phase shift branch. We propose to use first-order lattice all-pass filters with coupled inductors to create the required phase shifts, which offer more compact, wideband, and predictable results compared to conventional lattice all-pass filters with two separate inductors. We also propose to use four identical first-order lattice cells in reciprocal and nonreciprocal branches. This can further reduce the size of the nonreciprocal branch due to fewer inductors compared to a typical second-order all-pass filter like bridged-T. The circuit is implemented in a 28 nm CMOS process, and the active die area is only $0.17~\text {mm}^{{2}}$ . Our measurements demonstrate that the implemented circulator operates over a 1 dB insertion loss bandwidth of 14–28 GHz that achieves 66% fractional bandwidth with an insertion loss of 3.8 dB, isolation of over 20 dB, and input third-order intercept point of +19 dBm. - Samuel-Visal Roeung
Sähkötekniikan korkeakoulu | Bachelor's thesis(2021-05-10) Roeung, Samuel