Browsing by Author "Miettinen, Pekka"

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  • CAD:n soveltaminen osaksi laivan sisustussuunnittelua
    (1987) Miettinen, Pekka
     Helsinki University of Technology | Master's thesis
  • Compartmention structures in fire risk management
    (1994) Miettinen, Pekka
     Helsinki University of Technology | Master's thesis
  • Hierarchical model-order reduction tool for RLC circuits
    (2007) Miettinen, Pekka
     Helsinki University of Technology | Master's thesis
    Tämä työ käsittelee malliredusointia varten kehitetyn työkaluohjelmiston tutkimusta ja toteutusta. Kyseinen reduktiotyökalu kehitettiin suurikokoisten teollisten lineaaristen piirien, tai epälineaaristen piirien lineaaristen lohkojen, simuloinnin helpottamiseen, ja se kykenee erottelemaan tähän tarkoitukseen kelpaavat lineaariset RLC-osiot tyypillisestä SPICE-piirikuvauksesta. Reduktio suoritetaan käyttäen kyseiseen lohkoon parhaiten sopivaa algoritmia. Työkaluun sisällytetyt reduktioalgoritmit ovat PRIMA, Liao-Dai ja TICER. Kahta jälkimmäistä voidaan käyttää, jos piiri sisältää vain RC-elementtejä, kun taas PRIMA:a käytetään, jos lohko sisältää myös induktansseja. Reduktioprosessi suoritetaan lisäksi hierarkisesti, joka yleensä nopeuttaa käsittelyä huomattavasti.
  • Lineaaristen piirien malliredusointi
    (2014-05-11) Hällström, Lassi
     Sähkötekniikan korkeakoulu | Bachelor's thesis
  • Partitioning and macromodel-based model-order reduction for RLC circuits
    (2010) Miettinen, Pekka
     School of Electrical Engineering | Licentiate thesis
    This thesis details research and development of partitioning-based model-order reduction (MOR) for linear RLC circuits. Additionally, nonlinear circuits can be processed by extracting the linear RLC parts from the complete circuit. By using reduction, large circuits can be approximated with smaller circuits to speed up and help their simulation. Using partitioning in MOR to first partition the circuit into subcircuits makes it possible to use simple low-order approximations (macromodels) per each partition. On the other hand, when the approximated partitions are recombined after the reduction, high accuracy can be reached, if the original partitions are small. By using low-order macromodels, numerical problems typical to direct (outdated) high-order methods can be avoided and, thanks to partitioning, hierarchical analysis can he applied in a natural manner to further facilitate the reduction process. It is shown, in this thesis that by combining partitioning, low-order approximation, and the hierarchical approach, robust MOR algorithms can be obtained. First, two realizable MOR methods suitable for RC (-circuit)-in -RC (-circuit)-out and RL-in -RL-out reduction are presented. Then, a general-purpose, RLC-in -RLC-out MOR method, PartMQR, is presented. Comparison to existing MOR techniques is discussed with each method. Here, it is shown that the presented methods are well comparable with or clearly outperform the existing approaches for the cases shown.
  • Partitioning and macromodeling -based realizable reduction of interconnect circuit models
    (2014) Miettinen, Pekka
     School of Electrical Engineering | Doctoral dissertation (article-based)
    With advancing technology of integrated circuits, the interconnects and their non-ideal parasitics between active elements play an increasingly important role for the signal behavior. In a typical design flow, extraction tools are often used to generate a circuit netlist from the original chip topology for post-layout verification simulations. To reach desired accuracy, the interconnects and their parasitics need to be modeled with high precision that generates huge RLCK netlists, which in turn poses significant run-time and memory problems for the design process. One avenue to speed up the verification step is to apply model-order reduction (MOR) algorithms to the extracted netlists attempting to model the system with a reduced-size representation. This thesis details the research of partitioning and macromodel-based MOR approach for linear RLCK circuits. Using partitioning in MOR to first divide the circuit into smaller subcircuits makes it possible to use low-order approximations per each partition and still retain a good overall approximation accuracy for the total reduced circuit, when the individually reduced partitions are recombined. This use of low-order approximations in turn guarantees numerical stability and allows the approximations to be matched with relatively simple positive-valued RLCK macromodels, resulting in a realizable RLCK-in-RLCK-out reduction. Partitioning is known to provide the MOR also many other benefits, such as block-level sparsity, facilitated terminal node handling, reduced computational memory demands, and an option for natural parallel processing. Thanks to the many desirable features provided, this thesis aims to show that the presented MOR approach is highly efficient and well comparable to previously published MOR methods, especially in the case of typical interconnect RLCK circuits. The publications of this thesis first discuss the development of efficient RC and RL MOR methods, and the hierarchical approach to MOR offered by partitioning. Then, an RLC MOR method, PartMOR, using the same approach is presented. The latter four publications of this thesis focus on refining the presented methods and solving common difficulties in MOR: Singularity-generating structures in the original circuit can be avoided by isolating such structures with partitioning. Dense coupling of mutual inductances and capacitances between interconnects can be reduced with partitioning and a two-stage approximation. Finally, combining the presented methods together results in a complete RLCK-in-RLCK-out MOR algorithm package.