Aaltodoc Repository :: Browsing by Author "Lemberg, Jerry"

Browsing by Author "Lemberg, Jerry"

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A 0.35-to-2.6GHz multilevel outphasing transmitter with a digital interpolating phase modulator enabling up to 400MHz instantaneous bandwidth
(2017-03-02) Kosunen, Marko; Lemberg, Jerry; Martelius, Mikko; Roverato, Enrico; Nieminen, Tero; Englund, Mikko; Stadius, Kari; Anttila, Lauri; Pallonen, Jorma; Valkama, Mikko; Ryynänen, Jussi; Department of Electronics and Nanoengineering; Department of Micro and Nanosciences; Jussi Ryynänen Group; Nokia; Tampere University of Technology
Advanced wireless radio standards set stringent requirements on the bandwidth, frequency range and reconfigurability of base-station transmitters. Recently, the outphasing concept has shown promise of wide bandwidth while taking advantage of process scaling with extensive exploitation of rail-to-rail signaling. Recent outphasing transmitter designs have often focused on power-amplifier (PA) and power-combiner implementations while omitting the phase modulator [1,2]. Moreover, previously reported transmitters with integrated digital phase modulators have only shown bandwidths up to 40MHz [3,4], although 133MHz has been demonstrated at 10GHz carrier frequency utilizing phase modulators based on conventional IQ-DACs [5]. Thus, digital-intensive outphasing transmitters capable of modulation with hundreds of MHz bandwidth at existing cellular frequency bands have not yet been published. To address the aforementioned challenge, this paper introduces a multilevel outphasing transmitter with four amplitude levels, including the first prototype implementation based on the digital interpolating phase modulator concept [6]. The transmitter is targeted for 5G picocell base stations and has been verified to operate with instantaneous bandwidth up to 400MHz. In addition, the developed phase modulator eliminates the need for complex on-chip frequency synthesizers by introducing digital carrier frequency generation, demonstrated between 0.35 and 2.6GHz, while utilizing a single 1.8GHz reference clock.
A 1.5-1.9-GHz all-digital tri-phasing transmitter with an integrated multilevel class-D power amplifier achieving 100-MHz RF bandwidth
(Institute of Electrical and Electronics Engineers, 2019-06-01) Lemberg, Jerry; Martelius, Mikko; Roverato, Enrico; Antonov, Yury; Nieminen, Tero; Stadius, Kari; Anttila, Lauri; Valkama, Mikko; Kosunen, Marko; Ryynänen, Jussi; Department of Electronics and Nanoengineering; Jussi Ryynänen Group; Tampere University
We present a prototype RF transmitter with an integrated multilevel class-D power amplifier (PA), implemented in 28-nm CMOS. The transmitter utilizes tri-phasing modulation, which combines three constant-envelope phase-modulated signals with coarse amplitude modulation in the PA. This new architecture achieves the back-off efficiency of multilevel outphasing, without linearity-degrading discontinuities in the RF output waveform. Because all signal processing is performed in the time domain up to the PA, the entire system is implemented with digital circuits and structures, thus also enabling the use of synthesis and place-and-route CAD tools for the RF front end. The effectiveness of the digital tri-phasing concept is supported by extensive measurement results. Improved wideband performance is validated through the transmission of orthogonal frequency-division multiplexing (OFDM) bandwidths up to 100 MHz. Enhanced reconfigurability is demonstrated with non-contiguous carrier aggregation and digital carrier generation between 1.5 and 1.9 GHz without a frequency synthesizer. For a 20-MHz 256-QAM OFDM signal at 3.5% error vector magnitude (EVM), the transmitter achieves 22.6-dBm output power and 14.6% PA efficiency. Thanks to the high linearity enabled by tri-phasing, no digital predistortion is needed for the PA.
A 30-dBm class-D power amplifier with on/off logic for an integrated tri-phasing transmitter in 28-nm CMOS
(2018-08-07) Martelius, Mikko; Stadius, Kari; Lemberg, Jerry; Roverato, Enrico; Nieminen, Tero; Antonov, Yury; Anttila, Lauri; Valkama, Mikko; Kosunen, Marko; Ryynanen, Jussi; Department of Electronics and Nanoengineering; Jussi Ryynänen Group; Tampere University of Technology; CoreHW Oy
This paper presents an eight-unit class-D power amplifier (PA), implemented in 28-nm CMOS. The PA is designed to utilize tri-phasing modulation, which combines coarse-amplitude polar modulation with fine-resolution outphasing components. This new technique enables achieving the back-off efficiency of multilevel outphasing without linearity-degrading discontinuities in the output waveform. Each PA unit contains a cascoded output stage with a 3.6-V supply voltage, and on/off logic enabling multilevel operation controlled by low-voltage signals. The PA achieves a peak output power of 29.7 dBm with a 34.7% efficiency, and is verified to operate with aggregated LTE signals at bandwidths up to 60 MHz at 1.7-GHz carrier frequency.
A Class-D Tri-Phasing CMOS Power Amplifier with an Extended Marchand-Balun Power Combiner
(IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2020-03-01) Martelius, Mikko; Ryynanen, Jussi; Stadius, Kari; Lemberg, Jerry; Roverato, Enrico; Nieminen, Tero; Antonov, Yury; Anttila, Lauri; Valkama, Mikko; Kosunen, Marko; Department of Electronics and Nanoengineering; Jussi Ryynänen Group; Tampere University
This article presents a power amplifier (PA) design, which consists of eight class-D PA units on a single 28-nm CMOS die and a coupled-line power combiner on printed circuit board. The PA utilizes tri-phasing modulation, which combines polar and outphasing components in a way that eliminates linearity-degrading effects of multilevel outphasing while maintaining the back off efficiency. Each PA unit contains a cascoded output stage with a 3.6-V supply voltage, and multilevel operation is enabled by ON/OFF logic circuitry. Our analysis shows that the choice of power-combiner type is vital for reducing PA supply and ground ripple and thus ensuring reliable operation. Accordingly, the power combiner is implemented with extended Marchand baluns, which consist of input transmission lines and coupled-line sections. Unlike the original Marchand balun, our new topology is feasible for implementation under the layout restrictions caused by the multiple-unit PA on a single die. Measurement results show the PA achieving a peak output power of 29.7 dBm with a 34.7% efficiency, and operation with aggregated Long Term Evolution (LTE) signals at 1.7-GHz carrier frequency is verified with bandwidths up to 100 MHz.
A configurable sampling rate converter for all-digital 4G transmitters
(2013) Roverato, Enrico; Kosunen, Marko; Lemberg, Jerry; Nieminen, Tero; Stadius, Kari; Ryynänen, Jussi; Eloranta, Petri; Kaunisto, Risto; Pärssinen, Aarno; Department of Micro and Nanosciences; Jussi Ryynänen Group
Design and Implementation of a Wideband Digital Interpolating Phase Modulator RF Front-End
(2018-04-26) Lemberg, Jerry; Kosunen, Marko; Nieminen, Tero; Roverato, Enrico; Martelius, Mikko; Stadius, Kari; Ryynänen, Jussi; Anttila, Lauri; Valkama, Mikko; Department of Electronics and Nanoengineering; Jussi Ryynänen Group; Tampere University of Technology
This paper describes implementation details of a digital-intensive phase modulator architecture that does not require a frequency synthesizer to cover a wide carrier frequency range. The phase modulator operation is based on toggling the output accurately during the sample period to generate the phase-modulated signal. The toggling instants within the sample period are calculated by DSP solvers that utilize linear interpolation. The interpolation effectively multiplies the phase signal sample rate by the modulator phase resolution, which enables wider signal bandwidth and a completely digital method of defining the transmitter carrier frequency. The phase modulator concept is verified by implementing it as a part of an outphasing transmitter in 28 nm CMOS. With a constant sample rate of 1.5 GHz and without any predistortion, the transmitter achieves better than -28 dBc ACLR with 100 MHz aggregated LTE downlink signal between 0.8-2.0 GHz carrier frequency.
Digital Interpolating Phase Modulator for Wideband Outphasing Transmitters
(2016-03-23) Lemberg, Jerry; Kosunen, Marko; Roverato, Enrico; Martelius, Mikko; Stadius, Kari; Anttila, Lauri; Valkama, Mikko; Ryynänen, Jussi; Department of Micro and Nanosciences; Jussi Ryynänen Group; Tampere University of Technology
Radio transmitters are evolving towards digital-intensive solutions to exploit reconfigurability and benefit from CMOS process scaling. Outphasing has been identified as a suitable candidate for digital wideband transmitters. However, with recent digital-intensive outphasing transmitters the achieved performance in terms of adjacent channel leakage ratio (ACLR) has been limited. This paper identifies the sampling images of the modulating phase signal as the main factor limiting the ACLR of digital outphasing transmitters. We present a new digital interpolating phase modulator architecture, capable of providing significantly better sampling image attenuation. When evaluated in outphasing configuration with a 100 MHz OFDM signal at the carrier frequency of 2.46 GHz, and 10-bit phase resolution, the proposed solution achieves an ACLR of −59 dBc, compared to −43 dBc achievable with the phase modulator architecture utilized in state-of-the-art digital outphasing transmitters. The proposed digital interpolating phase modulator is also capable of custom carrier generation, a straightforward method for generating an arbitrary carrier frequency up to 1.25 times the phase modulator sampling rate.
A High-Speed DSP Engine for First-Order Hold Digital Phase Modulation in 28-nm CMOS
(2018) Roverato, Enrico; Kosunen, Marko; Lemberg, Jerry; Martelius, Mikko; Stadius, Kari; Anttila, Lauri; Valkama, Mikko; Ryynanen, Jussi; Department of Electronics and Nanoengineering; Jussi Ryynänen Group; Tampere University of Technology
Conventional delay-based digital phase modulators use a zero-order hold (ZOH) phase control word to modulate the square-wave RF carrier. Recently, new architectures capable of performing first-order hold (FOH) digital phase modulation have been proposed, thus improving the wideband performance to a level suitable for 5G base stations. While currently available literature focuses on the generic operation principle, this brief details the first on-chip implementation of the DSP engine required for actual FOH computations. The circuit is based on a simple iterative algorithm, which can be pipelined for high-speed operation. The DSP engine has been integrated as part of a prototype 5G base-station outphasing transmitter, fabricated in 28-nm CMOS. When processing a 100-MHz orthogonal frequency-division multiplexing signal, the DSP achieves an adjacent-channel leakage ratio of –53 dBc, which is 12 dB better than with conventional ZOH phase modulation. Furthermore, the system enables flexible upconversion to any frequency between 0.35 and 2.1 GHz from a fixed 1.5-GHz reference clock. The power consumption of a single engine is lower than 18 mW.
Integrated Digital-Intensive RF Transmitters
(Aalto University, 2018) Lemberg, Jerry; Kosunen, Marko, Dr., Aalto University, Department of Electronics and Nanoengineering, Finland; Elektroniikan ja nanotekniikan laitos; Department of Electronics and Nanoengineering; Sähkötekniikan korkeakoulu; School of Electrical Engineering; Ryynänen, Jussi, Prof., Aalto University, Department of Electronics and Nanoengineering, Finland
The emerging 5G radio standard aims to significantly improve the existing cellular network by increasing the achievable datarate and by decreasing response time. Achieving these improvements in the 5G network also necessitate new innovations in radio transmitter design. Integrated circuits and CMOS process scaling enable the inclusion of new features in a smaller area while simultaneously decreasing power consumption. Current trend in integration leads towards "system-on-chip" design methodology, where complex circuit entities are integrated on a single chip. Integration of radio transmitters is typically desired, as modern smartphones need to support several different communication standards that operate on different frequency bands. In the past, several parallel radio transmitter front ends have been designed on a chip to improve the level of integration. Since then, radio transmitter design has been driven by the software defined radio paradigm, which targets a single transmitter front end that can be digitally controlled to use the desired communication standard and frequency band. Outphasing modulation is a digital-intensive and energy efficient transmitter architecture and is thus a potential candidate for future software defined radio transmitters. This work presents a new digital-intensive phase modulator architecture that can improve the performance of outphasing-based transmitters by taking advantage of linear phase interpolation in digital domain. The proposed phase modulator enables improved outphasing transmitter linearity, and enables free carrier frequency selection without a frequency synthesizer. This work presents a prototype outphasing transmitter implemented in 28 nm CMOS that utilizes the proposed phase modulator architecture. The transmitter is demonstrated to operate between 0.8-2.0 gigahertz carrier frequency using constant 1.5 GHz reference clock, without a frequency synthesizer. The efficiency of outphasing transmitters can be further improved by using the multilevel outphasing transmitter architecture. It is shown in this work that discrete amplitude transitions that are inherent to multilevel outphasing architecture distort the transmitted signal. This work presents a new tri-phasing architecture that has been developed to alleviate the distortion caused by discrete amplitude transitions, while providing similar efficiency as multilevel outphasing. Furthermore, this work also presents a multilevel outphasing transmitter implemented in 28 nm CMOS, which enables up to 400 MHz OFDM signal bandwidth, a 10x improvement to state-of-the-art. This work also presents a prototype tri-phasing transmitter with integrated power amplifiers in 28 nm CMOS, which enables 100 MHz OFDM signal bandwidth at 1.7 GHz center frequency at 19 dBm output power while achieving -28dBc ACLR.
RIAA-korjaimen esivahvistimen suunnittelu ja toteutus
(2010) Lemberg, Jerry; Heikkinen, Sanna; Elektroniikan, tietoliikenteen ja automaation tiedekunta; Turunen, Markus
RX-Band Noise Reduction in All-Digital Transmitters With Configurable Spectral Shaping of Quantization and Mismatch Errors
(2014) Roverato, Enrico; Kosunen, Marko; Lemberg, Jerry; Stadius, Kari; Ryynänen, Jussi; Department of Micro and Nanosciences; Jussi Ryynänen Group
Spectral Effects of Discrete-Time Amplitude Levels in Digital-Intensive Wideband Radio Transmitters
(2018-05-04) Martelius, Mikko; Stadius, Kari; Lemberg, Jerry; Roverato, Enrico; Kosunen, Marko; Ryynänen, Jussi; Anttila, Lauri; Valkama, Mikko; Department of Electronics and Nanoengineering; Jussi Ryynänen Group; Tampere University of Technology
This paper examines one source of spectral degradation in polar and multilevel outphasing transmitters. The degradation is caused by the amplitude signal appearing at the transmitter output as a baseband component, in addition to the desired RF signal. This baseband component contains sampling images and quantization noise across the spectrum. Thus, it adds noise at the signal band where it cannot be filtered and limits the achievable ACLR, particularly in wideband LTE and 5G systems. We analyze the origin of this phenomenon and related effects of system and signal parameters, and propose three design solutions for eliminating or alleviating the problem. Our analysis and simulations demonstrate that using a voltage-subtracting power combiner cancels the described degradation, potentially leading to significant improvement in spectral performance.
Timing calibration for up-converting DAC
(2015-05-11) Azimirad, Arash; Stadius, Kari; Lemberg, Jerry; Sähkötekniikan korkeakoulu; Ryynänen, Jussi
This thesis deals with the timing error problem that appears in high frequency Digital to Analog Converters. Inequalities among signal paths in different branches and inaccuracies happened during fabrication, result in different time delays in different branches of a Digital to Analog Converter. The consequence of this inequality is having the data for different bits not arriving to the summation point at the same time. This timing error will create some glitches in the output analog signal. A new approach is introduced in this work that measures the timing error among branches of the DAC and corrects them through a calibration process. Being all the error measurement and its correction process done on chip, this approach can correct the errors created by both sources. This idea was implemented and tested in Eldo simulator. A timing error of 8pS was inserted to the MSB branch of a 10-bit binary coded DAC. After performing the calibration process on this DAC, the SFDR of the output signal was increased by about 3.2dB.
Tri-Phasing Modulation for Efficient and Wideband Radio Transmitters
(2018-09) Lemberg, Jerry; Martelius, Mikko; Kosunen, Marko; Roverato, Enrico; Stadius, Kari; Anttila, Lauri; Valkama, Mikko; Ryynanen, Jussi; Department of Electronics and Nanoengineering; Jussi Ryynänen Group; Tampere University of Technology
In this paper, we show that amplitude transitions that are inherent to the multilevel outphasing radio transmitter architecture distort the transmitted signal due to time-domain discontinuities. In order to address this challenge, we propose a new transmitter architecture called tri-phasing which avoids discontinuities in signal waveforms and thus achieves significantly better linearity than multilevel outphasing. The output waveform in tri-phasing can be made continuous by representing the baseband signal with three components. One of the three components is amplified by discrete amplitude steps, whereas the other two are used to compensate the instantaneous shift in the output waveform due to the discrete amplitude step and to provide fine amplitude resolution. An implementation of the tri-phasing transmitter requires three phase modulators and additional digital signal processing. The system-level simulations performed in this paper demonstrate that the ACLR of a multilevel outphasing transmitter with 4 amplitude levels and 10-bit phase resolution is limited to -48 dBc, when simulated with a 100 MHz carrier-aggregated LTE downlink signal at 2.46 GHz carrier frequency. The proposed tri-phasing transmitter achieves -58 dBc ACLR with the same simulation parameters, indicating that continuous amplitude transitions can significantly improve the transmitter linearity.
Ylössekoittava digitaali-analogiamuunnin
(2013-11-18) Lemberg, Jerry; Stadius, Kari; Sähkötekniikan korkeakoulu; Ryynänen, Jussi
Tämä diplomityö tehtiin osana tutkimusprojektia, jossa tarkoituksena oli suunnitella lähetinpiiri LTE radioverkoille. Tutkimustyö on tehty yhdessä Enrico Roveraton kanssa, jonka diplomityössä kuvataan projektin syysteemitason suunnittelu, sekä digitaalisen esiasteen toteutus. Osana digitaalista esiastetta on kohinanmuokkain, jolla pyritään madaltamaan vastaanottimen kaistan kohinatasoa jottei SAW-suodattimia tarvita. Tämän työn keskeisin osa on suoraan kantoaallolle ylössekoittavan 10-bittisen segmentoidun digitaali-analogiamuuntimen (RF-DAC) suunnittelu. Muuntimella vältetään suuri osa tavanomaista suoramuunnoslähetintä vaivaavista analogisen signaalinkäsittelyn ongelmista korvaamalla perinteiset analogiset operaatiot digitaalisilla vastineillaan. Suunnitellussa lähettimessä tarvitaan vain yksi digitaali-analogiamuunnin, jolloin tyypillisesti kahden muuntimen välillä olevat amplitudi-, ja vaiheongelmat voidaan välttää. Valitun lähetinarkkitehtuurin ongelmat kulminoituvatkin lähtöasteen amplitudi-, ja ajoitusvirheisiin. Työssä esitetään myös miten kohinanmuokkaimen vaatima lineaarisuus on kuitenkin hyvin haastava toteuttaa valitunlaisella lähetinarkkitehtuurilla, sillä korkean näytteistystaajuuden omaavan digitaalianalogiamuuntimen ajoitusvirheet johtavat signaalin liialliseen säröytymiseen. Työssä esitetty lähetin kykenee ylössekoittamaan kaksi 10-bittistä, 20MHz:n digitaalisesti muokattua kantataajuussignaalia 2 GHz:n taajuudelle 10 dBm:n lähtöteholla käyttäen vain 165 mW.

Browsing by Author "Lemberg, Jerry"

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