Browsing by Author "Lahtinen, Veeti"
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- An Automated EM-Simulation Environment with Parameterized Layout Generation for Microwave Integrated Circuits
A4 Artikkeli konferenssijulkaisussa(2023) Ryynanen, Kaisa; Lahtinen, Veeti; Porrasmaa, Santeri; Stadius, Kari; Kosunen, Marko; Ryynanen, JussiDesign automation of microwave components is increasing its importance in sub-THz applications such as fifth (5G) and sixth generation (6G) communications and sensing applications. Sub-THz design involves laborious, tedious and time-consuming iterative trial-and-error work present in typical electromagnetic design flows used for microwave circuits. To eliminate the need for manual iterations, this paper introduces an automated design environment, which enables seamless integration of these components to traditional tool-chains in integrated circuits. The implementation uses Berkeley Analog Generator (BAG) for programmatic layout generation, ADS Momentum applied as an electromagnetic (EM) field simulator, and The System Development Kit (TheSyDeKick) multi-simulator system design and verification environment. In this work, a new open-source ADS Momentum TheSyDeKick simulation interface has been implemented to bind the two former together which enables large-scale optimization of microwave components. The advantage of using the design environment is demonstrated by generating and simulating 260 interwound and 104 stacked transformers in a loop to find the optimum for 100 GHz. - Digital-to-analog conversion in wideband digital polar transmitters
Sähkötekniikan korkeakoulu | Master's thesis(2023-03-20) Lahtinen, VeetiThe ongoing deployment of 5G devices has led to an increased demand for highly integrated power efficient wideband transmitters. This, alongside the complementary metal oxide semiconductor process evolution, is favouring digitally intensive transmitter architectures. Therefore, polar transmitters have been an interesting research topic due to the digitally intensive phase modulation and the ability to use switched-mode power amplifiers. However, full potential of the architecture has not yet been realized, with the state-of-the-art implementations suffering from limited bandwidths up to 160 megahertz. This thesis evaluates the feasibility of polar transmitters for even wider bandwidth signal transmission, mainly focusing on the digital-to-analog conversion. The feasibility is investigated in two parts, a literature review on the state-of-the-art and a developed polar transmitter model. The literature review compares the polar architecture to the other commonly used alternatives. Furthermore, the most common digital-to-analog conversion methods and key figures of merit are introduced. The developed polar transmitter model has all of the core building blocks required for a polar transmitter modelled in Python using The System Development Kit (TheSyDeKick) development and verification platform. Additionally, the digital-to-analog converter is implemented as two schematic models selected from the literature survey. The schematics are written as fully parameterized schematic generators using Berkeley Analog Generator (BAG), which is a framework written in Python for programmatic layout and schematic generation. The polar transmitter model is used to investigate resolutions required to theoretically match communications signal standards with wideband signals. Full transmitter model simulations with 5G signals with varying carrier frequencies are then run on a developed simulation testbench to the different implemented digital-to-analog converter models. The results are then compared and analyzed. By studying, modelling and simulating the architecture, the thesis concludes that the polar transmitter architecture is capable of wideband signal transmission. The simulated bandwidths are wider than previously presented in the state-of-the-art implementations. The bandwidth limitation is found to be mainly due to the bandwidth expansion of the signal component separation posing challenges to the phase modulator. As a result, the digital-to-analog converter is found to be less of a limiting factor. - Low-Voltage Differential Signaling Transceiver for High-speed Serial Links
Sähkötekniikan korkeakoulu | Bachelor's thesis(2023-12-08) Mäki, Miikka - Measurement Automation of Integrated Circuits with Python
Sähkötekniikan korkeakoulu | Bachelor's thesis(2020-12-01) Lahtinen, Veeti - Procedural Design, Verification and Implementation Framework for Analog Amplifiers
A4 Artikkeli konferenssijulkaisussa(2024-06-03) Lahtinen, Veeti; Porrasmaa, Santeri; Kosunen, Marko; Ryynänen, JussiThis paper presents a modular, parasitic-aware, process agnostic design and verification procedure. The procedure utilizes TheSyDeKick simulation and verification framework in combination with Berkeley Analog Generator (BAG). BAG is utilized to programmatically construct the schematic and layout in order to provide the parasitic component information for the algorithmic optimization procedure. This enables the most accurate definition of transistor sizing parameters to obtain the desired linearity, speed and noise performance. As the generation, extraction and design procedures are fully automated, this remarkably speeds up the design exploration. The presented procedural optimization is extensible to wide range of analog building blocks, and the effectiveness of method is demonstrated in context of a single-stage operational transconductance amplifier (OTA). The proposed method incorporates an algorithm that automatically sizes the design to achieve minimal current consumption for a given speed specification and provides a manufacturing-ready circuit implementation. The algorithm is demonstrated to effectively converge on final designs for various speed specifications with two distinct semiconductor processes.