Browsing by Author "Korhonen, Teuvo"

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  • A 100–750 MS/s 11-Bit Time-to-Digital Converter With Cyclic-Coupled Ring Oscillator
    (2021-03-24) Jarvinen, Okko; Unnikrishnan, Vishnu; Siddiqui, Waqas; Korhonen, Teuvo; Koli, Kimmo; Stadius, Kari; Kosunen, Marko; Ryynanen, Jussi
     A1 Alkuperäisartikkeli tieteellisessä aikakauslehdessä
    This paper presents the first measured cyclic-coupled ring oscillator (CCRO) time-to-digital converter (TDC). The CCRO realizes a robust true time-domain delay interpolation with sub-gate-delay resolution. The architecture employs real-time quantization to reduce conversion time and hence maximize bandwidth. Furthermore, the CCRO phase progression is encoded with a bubble error suppression logic, thereby building resilience to delay mismatches from circuit/layout imperfections. The prototype circuit implemented in a 28 nm CMOS process demonstrates a combination of high resolution and high sample rate over wide range of sample rates. The TDC achieves its peak figure-of-merit (FoM) of 0.051 pJ/conv.-step at 100 MS/s while delivering 8.38-bit linear resolution and 15.4 ps time resolution, operating from a 0.55 V supply. The TDC demonstrates the highest reported linear resolution of 9.29 bits among converters operating above 100 MS/s, at 125 MS/s and 0.9 V supply, while achieving 4.4 ps time resolution and 0.16 pJ/conv.-step FoM. Further, the real-time quantizing architecture allows fast operation up to 750 MS/s, where the TDC delivers 6-bit linear resolution and 0.48 pJ/conv.-step FoM operating from 0.9 V supply.
  • All-Digital LTE SAW-Less Transmitter With DSP-Based Programming of RX-Band Noise
    (2017-11-21) Roverato, Enrico; Kosunen, Marko; Cornelissens, Koen; Vatti, Sofia; Stynen, Paul; Bertrand, Kaoutar; Korhonen, Teuvo; Samsom, Hans; Vandenameele, Patrick; Ryynanen, Jussi
     A1 Alkuperäisartikkeli tieteellisessä aikakauslehdessä
    We present the first all-digital LTE transmitter (TX) using programmable digital attenuation of receive band (RX-band) noise. The system is architectured to fully exploit the speed and low cost of DSP logic in deep-submicrometer CMOS processes, without increasing at all the design effort of the RF circuitry. To achieve operation without surface acoustic wave filter, the TX uses digital bandpass delta-sigma modulation and mismatch-shaping to attenuate the DAC noise at a programmable duplex distance. These functions can be implemented entirely within DSP, thus taking advantage of the standard digital design methodology. Furthermore, the fully digital RX-band noise shaping significantly relaxes the performance requirements on the RF front-end. Therefore, 10 bits of resolution for the D/A conversion are sufficient to achieve -160 dBc/Hz out-of-band (OOB) noise, without need for digital predistortion, calibration, or bulky analog filters. The TX was fabricated in 28-nm CMOS, and occupies only 0.82 mmsuperscript2. Besides low OOB noise, our system also demonstrates state-of-art linearity performance, with measured CIM3/CIM5 below -67 dBc, and adjacent-channel leakage ratio of -61 dBc with LTE20 carrier. The circuit consumes 150 mW from 0.9-/1.5-V supplies at +3 dBm output power.
  • All-digital RF transmitter in 28nm CMOS with programmable RX-band noise shaping
    (2017-03-02) Roverato, Enrico; Kosunen, Marko; Cornelissens, Koen; Vatti, Sofia; Stynen, Paul; Bertrand, Kaoutar; Korhonen, Teuvo; Samsom, Hans; Vandenameele, Patrick; Ryynänen, Jussi
     A4 Artikkeli konferenssijulkaisussa
    The crowded radio spectrum allocated for 3G/4G mobile communication, together with the growing demand for higher data-rates, has led to the situation where transceivers need to support FDD operation in multiple frequency bands with different TX-RX duplex spacing. In order to reduce costs and enable SAW-less operation, many recent transmitter implementations have thus targeted stringent out-of-band (OOB) emission levels. Analog-intensive TX architectures achieve low OOB noise at the price of large area consumption, as complex reconstruction filters are used to suppress DAC quantization noise and image replicas [1,2]. On the other hand, due to the lack of analog filtering, digital-intensive TX architectures need 12-14b DAC resolution for low OOB noise, which complicates DAC design and typically requires DPD or calibration [3-5]. This work presents an RF transmitter implementing a fully digital solution to the aforementioned challenge. Instead of using bulky analog filtering or high resolution DAC, the disclosed TX employs digital ΔΣ modulation and mismatch shaping to attenuate the DAC noise at a programmable duplex distance. This solution enables -160dBc/Hz noise in the RX-band, by using only a 10b DAC without DPD, calibration or analog filtering.
  • Power-Scalable Dynamic Element Matching for a 3.4-GHz 9-bit ΔΣ RF-DAC in 16-nm FinFET
    (2018) Roverato, E.; Kosunen, M.; Cornelissens, K.; Korhonen, Teuvo; Samsom, H.; Borremans, M.; Ryynänen, J.
     A1 Alkuperäisartikkeli tieteellisessä aikakauslehdessä
    This letter presents a hardware-efficient technique to scale the power consumption of dynamic element matching (DEM) DACs with the static back-off level of the digital input signal. Unlike previous DEM techniques, the proposed power-scalable approach disables parts of the DEM encoder and DAC elements when the digital signal level is decreased from full-scale, thus resulting in reduced power consumption and lower mismatch noise at the DAC output. Power-scalable DEM is particularly useful in digital-intensive RF transmitters, where 30–50 dB of signal power control may be performed in the digital domain. The concept is demonstrated for a 3.4-GHz 9-bit I/Q RF-DAC, utilizing bandpass delta–sigma modulation and DEM with programmable center frequency. The circuit is fabricated in a 16-nm FinFET process. When changing the digital back-off level of an LTE20 carrier from 0 to −18 dB, measurement results show a 72% reduction in total power consumption and 4.5-dB lower mismatch noise, achieved without performing any bias tuning or gain control in the analog domain. The digital delta–sigma modulator and DEM encoder consume less than 20 mW in full-scale mode.