Browsing by Author "Anttila, Lauri"

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A 0.35-to-2.6GHz multilevel outphasing transmitter with a digital interpolating phase modulator enabling up to 400MHz instantaneous bandwidth
(2017-03-02) Kosunen, Marko; Lemberg, Jerry; Martelius, Mikko; Roverato, Enrico; Nieminen, Tero; Englund, Mikko; Stadius, Kari; Anttila, Lauri; Pallonen, Jorma; Valkama, Mikko; Ryynänen, Jussi
A4 Artikkeli konferenssijulkaisussa
Advanced wireless radio standards set stringent requirements on the bandwidth, frequency range and reconfigurability of base-station transmitters. Recently, the outphasing concept has shown promise of wide bandwidth while taking advantage of process scaling with extensive exploitation of rail-to-rail signaling. Recent outphasing transmitter designs have often focused on power-amplifier (PA) and power-combiner implementations while omitting the phase modulator [1,2]. Moreover, previously reported transmitters with integrated digital phase modulators have only shown bandwidths up to 40MHz [3,4], although 133MHz has been demonstrated at 10GHz carrier frequency utilizing phase modulators based on conventional IQ-DACs [5]. Thus, digital-intensive outphasing transmitters capable of modulation with hundreds of MHz bandwidth at existing cellular frequency bands have not yet been published. To address the aforementioned challenge, this paper introduces a multilevel outphasing transmitter with four amplitude levels, including the first prototype implementation based on the digital interpolating phase modulator concept [6]. The transmitter is targeted for 5G picocell base stations and has been verified to operate with instantaneous bandwidth up to 400MHz. In addition, the developed phase modulator eliminates the need for complex on-chip frequency synthesizers by introducing digital carrier frequency generation, demonstrated between 0.35 and 2.6GHz, while utilizing a single 1.8GHz reference clock.
A 1.5-1.9-GHz all-digital tri-phasing transmitter with an integrated multilevel class-D power amplifier achieving 100-MHz RF bandwidth
(2019-06-01) Lemberg, Jerry; Martelius, Mikko; Roverato, Enrico; Antonov, Yury; Nieminen, Tero; Stadius, Kari; Anttila, Lauri; Valkama, Mikko; Kosunen, Marko; Ryynänen, Jussi
A1 Alkuperäisartikkeli tieteellisessä aikakauslehdessä
We present a prototype RF transmitter with an integrated multilevel class-D power amplifier (PA), implemented in 28-nm CMOS. The transmitter utilizes tri-phasing modulation, which combines three constant-envelope phase-modulated signals with coarse amplitude modulation in the PA. This new architecture achieves the back-off efficiency of multilevel outphasing, without linearity-degrading discontinuities in the RF output waveform. Because all signal processing is performed in the time domain up to the PA, the entire system is implemented with digital circuits and structures, thus also enabling the use of synthesis and place-and-route CAD tools for the RF front end. The effectiveness of the digital tri-phasing concept is supported by extensive measurement results. Improved wideband performance is validated through the transmission of orthogonal frequency-division multiplexing (OFDM) bandwidths up to 100 MHz. Enhanced reconfigurability is demonstrated with non-contiguous carrier aggregation and digital carrier generation between 1.5 and 1.9 GHz without a frequency synthesizer. For a 20-MHz 256-QAM OFDM signal at 3.5% error vector magnitude (EVM), the transmitter achieves 22.6-dBm output power and 14.6% PA efficiency. Thanks to the high linearity enabled by tri-phasing, no digital predistortion is needed for the PA.
An 18–28 GHz dual-mode down-converter IC for 5G applications
(2024-02) Naghavi, Saeed; Ryynänen, Kaisa; Zahra, Mahwish; Korsman, Aleksi; Stadius, Kari; Kosunen, Marko; Unnikrishnan, Vishnu; Anttila, Lauri; Valkama, Mikko; Ryynänen, Jussi
A1 Alkuperäisartikkeli tieteellisessä aikakauslehdessä
Emerging spectrum trends require a higher integration of 5G New Radio Frequency Range 1 (FR1) and Frequency Range 2 (FR2) bands to enhance the availability of spectrum and spectrum-sharing opportunities. To enable the reception of both FR1 and FR2 bands in a seamless hardware entity, we propose combining homodyne and heterodyne architectures. This necessitates the incorporation of a down-converter module that transfers the incoming signals from FR2 bands down to FR1, ensuring compatibility with an FR1 direct-conversion receiver (DCR) for the final signal reception. The primary focus of this paper is the design and implementation of the required integrated down-converter. The module includes an integrated balun, a low-noise amplifier (LNA) with a bypass mode, a dual-mode mixer, and an intermediate frequency (IF) amplifier. The introduced bypass mode helps to further elevate the linearity performance compared to the nominal mode. The bypass mode is designed for joint communication and sensing operation to avoid the compression of the receiver. This work also incorporates a local oscillator (LO) signal distribution network with phase tuning elements using a mixed-signal approach. The circuit is implemented in a 22-nm CMOS process, and the active die area is 0.6 mm 2 . The measurements demonstrate that the implemented chip can efficiently perform the required frequency conversion over a wide frequency range of 18–28 GHz. Conversion gain of 4.5–7.5 dB, noise figure of 15–19.7 dB, 1 dB compression point (IP1dB) of − 16 to − 10 dBm, and input third-order intercept point (IIP3) of − 5 to 0 dBm are achieved. The measured IP1 dB and IIP3 for the bypass mode are +0.5 to +4.5 dBm and +8.5 to +10 dBm, respectively.
A 2-5.5 GHz Beamsteering Receiver IC With 4-Element Vivaldi Antenna Array
(2020-09) Zahra, Mahwish; Kempi, Ilia; Haarla, Jaakko; Antonov, Yury; Khonsari, Zahra; Miilunpalo, Toni; Ahmed, Nouman; Inkinen, Juha; Unnikrishnan, Vishnu; Lehtovuori, Anu; Viikari, Ville; Anttila, Lauri; Valkama, Mikko; Kosunen, Marko; Stadius, Kari; Ryynänen, Jussi
A1 Alkuperäisartikkeli tieteellisessä aikakauslehdessä
In this article, we present a four-element Vivaldi antenna array and beamsteering receiver IC for the fifth-generation mobile network (5G) new radio (NR). The implemented receiver utilizes a delay-based local-oscillator phase shift technique for accurate beamsteering, and it exhibits 1° to 2.4° phase tuning capability for 2-5 GHz bandwidth accordingly. On-chip delay measurement is performed with pilot signal generation and delay estimation capable of 2-ps accuracy. The IC is fabricated on 28-nm CMOS technology, it occupies an area of 1.4x1.4 mm^2, including bonding pads, and consumes 22.8 mW at 2 GHz for single-receiver path operation. The receiver demonstrates wideband over-the-air reception with the prototype antennas.
A 30-dBm class-D power amplifier with on/off logic for an integrated tri-phasing transmitter in 28-nm CMOS
(2018-08-07) Martelius, Mikko; Stadius, Kari; Lemberg, Jerry; Roverato, Enrico; Nieminen, Tero; Antonov, Yury; Anttila, Lauri; Valkama, Mikko; Kosunen, Marko; Ryynanen, Jussi
A4 Artikkeli konferenssijulkaisussa
This paper presents an eight-unit class-D power amplifier (PA), implemented in 28-nm CMOS. The PA is designed to utilize tri-phasing modulation, which combines coarse-amplitude polar modulation with fine-resolution outphasing components. This new technique enables achieving the back-off efficiency of multilevel outphasing without linearity-degrading discontinuities in the output waveform. Each PA unit contains a cascoded output stage with a 3.6-V supply voltage, and on/off logic enabling multilevel operation controlled by low-voltage signals. The PA achieves a peak output power of 29.7 dBm with a 34.7% efficiency, and is verified to operate with aggregated LTE signals at bandwidths up to 60 MHz at 1.7-GHz carrier frequency.
A 30-GHz Switched-Capacitor Power Amplifier for 5G SoCs
(2020-11-23) Saleem, Ali Raza; Stadius, Kari; Kosunen, Marko; Anttila, Lauri; Valkama, Mikko; Ryynanen, Jussi
A4 Artikkeli konferenssijulkaisussa
Switched-capacitor power amplifier has gained popularity within the radio frequency integrated circuit community, since it is CMOS compatible offering high integration density and good performance particularly in terms of linearity. In this paper we present a study on the use of switched-capacitor power amplifier at millimeter-wave frequency range. We identify the major design challenges in this paper, and demonstrate the feasibility of switched-capacitor power amplifier with a 30-G Hz design case. Our analysis describes the effects of power amplifier device parasitics and their contribution to dynamic power consumption, revealing that these are a major factor in degradation of switched capacitor power amplifier efficiency at millimeter waves. Two circuits, one for 3 GHz and the other for 30 GHz, were designed and simulated with 28-nm bulk CMOS technology. At 3 GHz, the designed switched capacitor power amplifier structure with 6-bit resolution features maximum output power of 19.4 dBm and efficiency of 59% whereas the output power of 18.6 dBm with 21% efficiency is achieved at 30 GHz. The switched-capacitor power amplifier preserves its good linearity at higher frequencies as well, and our design demonstrates an adjacent channel leackage ratio of -34.4 dB at 30 GHz for a 100-MHz OFDM-modulated signal.
A 6–20 GHz 400-MHz Modulation-Bandwidth CMOS Transmitter IC
(2022-10-26) Saleem, Ali Raza; Naghavi, Saeed; Zahra, Mahwish; Stadius, Kari; Kosunen, Marko; Anttila, Lauri; Valkama, Mikko; Ryynänen, Jussi
A4 Artikkeli konferenssijulkaisussa
This paper presents a transmitter IC with two identical signal paths, including base-band amplifier, up-converting mixer, and power amplifier (PA) stages. The design is focused on wide modulation bandwidth, and the use of a resonatorless small die-area class-D power amplifier at cm-wave frequencies. This work also incorporates a local oscillator (LO) signal distribution network with phase tuning elements. The circuit is implemented in a 22-nm CMOS process, and the active die area is 0.8 mm2. Operation over the 6–20 GHz range of carrier frequencies through the transmission of both continuous wave (CW) and wideband quadrature phase shift keying (QPSK) modulated signals were verified with measurements. Results with 20/40/100, and 400 MHz modulation bandwidths are presented, and for instance for a 20-MHz QPSK modulated input signal the measured adjacent channel leakage ratio (ACLR) of the transmitter is 28 dBc and error vector magnitude (EVM) is 5%.
Adaptive Nonlinear RF Cancellation for Improved Isolation in Simultaneous Transmit-Receive Systems
(2018) Kiayani, Adnan; Waheed, Muhammad Zeeshan; Anttila, Lauri; Abdelaziz, Mahmoud; Korpi, Dani; Syrjala, Ville; Kosunen, Marko; Stadius, Kari; Ryynanen, Jussi; Valkama, Mikko
A1 Alkuperäisartikkeli tieteellisessä aikakauslehdessä
This paper proposes an active radio frequency (RF) cancellation solution to suppress the transmitter (TX) passband leakage signal in radio transceivers supporting simultaneous transmission and reception. The proposed technique is based on creating an opposite-phase baseband equivalent replica of the TX leakage signal in the transceiver digital front-end through adaptive nonlinear filtering of the known transmit data, to facilitate highly accurate cancellation under a nonlinear power amplifier (PA). The active RF cancellation is then accomplished by employing an auxiliary TX chain to generate the actual RF cancellation signal, and combining it with the received signal at the receiver (RX) low-noise amplifier (LNA) input. A closed-loop parameter learning approach, based on the decorrelation learning rule, is also developed to efficiently estimate the coefficients of the nonlinear cancellation filter in the presence of a nonlinear PA with memory, finite passive isolation, and a nonlinear LNA. The performance of the proposed cancellation technique is evaluated through comprehensive RF measurements adopting commercial LTE-Advanced transceiver hardware components. The results show that the proposed technique can provide an additional suppression of up to 54 dB for the TX passband leakage signal at the LNA input, even at very high transmit power levels and with wide transmission bandwidths. Such a novel cancellation solution can, therefore, substantially improve the TX-RX isolation, hence reducing the requirements on passive isolation and RF component linearity, as well as increasing the efficiency and flexibility of the RF spectrum use in the emerging 5G radio networks.
A Class-D Tri-Phasing CMOS Power Amplifier with an Extended Marchand-Balun Power Combiner
(2020-03-01) Martelius, Mikko; Ryynanen, Jussi; Stadius, Kari; Lemberg, Jerry; Roverato, Enrico; Nieminen, Tero; Antonov, Yury; Anttila, Lauri; Valkama, Mikko; Kosunen, Marko
A1 Alkuperäisartikkeli tieteellisessä aikakauslehdessä
This article presents a power amplifier (PA) design, which consists of eight class-D PA units on a single 28-nm CMOS die and a coupled-line power combiner on printed circuit board. The PA utilizes tri-phasing modulation, which combines polar and outphasing components in a way that eliminates linearity-degrading effects of multilevel outphasing while maintaining the back off efficiency. Each PA unit contains a cascoded output stage with a 3.6-V supply voltage, and multilevel operation is enabled by ON/OFF logic circuitry. Our analysis shows that the choice of power-combiner type is vital for reducing PA supply and ground ripple and thus ensuring reliable operation. Accordingly, the power combiner is implemented with extended Marchand baluns, which consist of input transmission lines and coupled-line sections. Unlike the original Marchand balun, our new topology is feasible for implementation under the layout restrictions caused by the multiple-unit PA on a single die. Measurement results show the PA achieving a peak output power of 29.7 dBm with a 34.7% efficiency, and operation with aggregated Long Term Evolution (LTE) signals at 1.7-GHz carrier frequency is verified with bandwidths up to 100 MHz.
A Delay-Based LO Phase-Shifting Generator for a 2-5GHz Beamsteering Receiver in 28nm CMOS
(2019) Antonov, Yury; Zahra, Mahwish; Stadius, Kari; Khonsari, Zahra; Kempi, Ilia; Miilunpalo, Toni; Inkinen, Juha; Unnikrishnan, Vishnu; Anttila, Lauri; Valkama, Mikko; Kosunen, Marko; Ryynänen, Jussi
A4 Artikkeli konferenssijulkaisussa
This paper proposes a wideband 2-5GHz LO phase-shifting generator based on two digitally controlled delay lines. The concept is verified on a two-channel beamsteering direct conversion receiver prototype implemented in 28nm CMOS. The novel generator provides both tunable phase-shifting and generation of I/Q components, achieving picosecond time resolution. The generator consumes 4.5-11.2mW and occupies 0.021mm.sq.
Design and Implementation of a Wideband Digital Interpolating Phase Modulator RF Front-End
(2018-04-26) Lemberg, Jerry; Kosunen, Marko; Nieminen, Tero; Roverato, Enrico; Martelius, Mikko; Stadius, Kari; Ryynänen, Jussi; Anttila, Lauri; Valkama, Mikko
A4 Artikkeli konferenssijulkaisussa
This paper describes implementation details of a digital-intensive phase modulator architecture that does not require a frequency synthesizer to cover a wide carrier frequency range. The phase modulator operation is based on toggling the output accurately during the sample period to generate the phase-modulated signal. The toggling instants within the sample period are calculated by DSP solvers that utilize linear interpolation. The interpolation effectively multiplies the phase signal sample rate by the modulator phase resolution, which enables wider signal bandwidth and a completely digital method of defining the transmitter carrier frequency. The phase modulator concept is verified by implementing it as a part of an outphasing transmitter in 28 nm CMOS. With a constant sample rate of 1.5 GHz and without any predistortion, the transmitter achieves better than -28 dBc ACLR with 100 MHz aggregated LTE downlink signal between 0.8-2.0 GHz carrier frequency.
Digital Interpolating Phase Modulator for Wideband Outphasing Transmitters
(2016-03-23) Lemberg, Jerry; Kosunen, Marko; Roverato, Enrico; Martelius, Mikko; Stadius, Kari; Anttila, Lauri; Valkama, Mikko; Ryynänen, Jussi
A1 Alkuperäisartikkeli tieteellisessä aikakauslehdessä
Radio transmitters are evolving towards digital-intensive solutions to exploit reconfigurability and benefit from CMOS process scaling. Outphasing has been identified as a suitable candidate for digital wideband transmitters. However, with recent digital-intensive outphasing transmitters the achieved performance in terms of adjacent channel leakage ratio (ACLR) has been limited. This paper identifies the sampling images of the modulating phase signal as the main factor limiting the ACLR of digital outphasing transmitters. We present a new digital interpolating phase modulator architecture, capable of providing significantly better sampling image attenuation. When evaluated in outphasing configuration with a 100 MHz OFDM signal at the carrier frequency of 2.46 GHz, and 10-bit phase resolution, the proposed solution achieves an ACLR of −59 dBc, compared to −43 dBc achievable with the phase modulator architecture utilized in state-of-the-art digital outphasing transmitters. The proposed digital interpolating phase modulator is also capable of custom carrier generation, a straightforward method for generating an arbitrary carrier frequency up to 1.25 times the phase modulator sampling rate.
Digital Polar Transmitters for Massive MIMO: Sum-Rate and Power Efficiency Analysis
(2024-01-01) Xu, Guixian; Lampu, Vesa; Kosunen, Marko; Unnikrishnan, Vishnu; Ryynanen, Jussi; Valkama, Mikko; Anttila, Lauri
A1 Alkuperäisartikkeli tieteellisessä aikakauslehdessä
In this article, we comprehensively investigate the potential of the digital polar radio transmitter architecture for multi-user massive multiple-input multiple-output orthogonal frequency-division multiplexing (MIMO-OFDM) downlink system. In terms of throughput performance, we derive a lower bound for the average sum-rate achievable with Gaussian signaling inputs and zero-forcing (ZF) precoding based on Bussgang decomposition. By diagonal approximation, we derive an approximate, yet accurate, model for the distortion caused by uniform polar quantization, which can be used to evaluate the corresponding sum-rate in closed form. To assess the power efficiency, we provide power consumption models with realistic parameters and values for the quantized polar and Cartesian transmitters, based on state-of-the-art integrated circuit (IC) designs and measurements. Extensive numerical results demonstrate that the proposed quantized polar transmitter can enable excellent performance in terms of average sum-rate, symbol error rate (SER), and out-of-band (OOB) emission level, compared to the Cartesian architecture. Furthermore, the power consumption comparisons show that the digital polar transmitter can save more than 36% in the energy consumption under 64-antenna setting in typical 5G enhanced mobile broadband use cases, thus making it highly appealing for future power-efficient massive MIMO transmitter implementations.
High-Precision Time-to-Digital Conversion for Calibration of Outphasing Radio Transmitters
(2023) Boopathy, Dhanashree; Cheung, Tze Hin; Spelman, Andrei; Ghosh, Agnimesh; Lampu, Vesa; Anttila, Lauri; Stadius, Kari; Kosunen, Marko; Ryynanen, Jussi; Unnikrishnan, Vishnu
A4 Artikkeli konferenssijulkaisussa
Wireless transceivers for 5G NR FR2 frequencies around 30 GHz support signal bandwidths up to 400 MHz to achieve ambitious data rates. The Phase Modulators (PMs) in the FR2 outphasing transmitters generates delays with delay steps of about a few hundred femtoseconds. To calibrate and linearize the PMs, time-to-digital converters (TDCs) that measure delays with higher accuracy in the order of a few femtoseconds are required. To this end, this work explores two synthesizable time interval averaging (TIA) TDCs which employ averaging to achieve a high accuracy with low-precision hardware. The results show that the delay quantization step of the converter has an effect only on the time taken to achieve the required accuracy, presenting opportunities to reduce area and power consumption. Simulation shows that a TDC with quantization step of 12.5 ns achieves an accuracy of 0.3 fs by averaging 2^28 samples. For a 32 GHz 7-bit PM producing a minimum delay step of 244 fs, this implies a TDC of 8-bit precision for each time step. The hardware synthesized towards a 22 nm FDSOI process occupies 0.0004 mm^2 area and consumes 0.3 mW power.
A High-Speed DSP Engine for First-Order Hold Digital Phase Modulation in 28-nm CMOS
(2018) Roverato, Enrico; Kosunen, Marko; Lemberg, Jerry; Martelius, Mikko; Stadius, Kari; Anttila, Lauri; Valkama, Mikko; Ryynanen, Jussi
A1 Alkuperäisartikkeli tieteellisessä aikakauslehdessä
Conventional delay-based digital phase modulators use a zero-order hold (ZOH) phase control word to modulate the square-wave RF carrier. Recently, new architectures capable of performing first-order hold (FOH) digital phase modulation have been proposed, thus improving the wideband performance to a level suitable for 5G base stations. While currently available literature focuses on the generic operation principle, this brief details the first on-chip implementation of the DSP engine required for actual FOH computations. The circuit is based on a simple iterative algorithm, which can be pipelined for high-speed operation. The DSP engine has been integrated as part of a prototype 5G base-station outphasing transmitter, fabricated in 28-nm CMOS. When processing a 100-MHz orthogonal frequency-division multiplexing signal, the DSP achieves an adjacent-channel leakage ratio of –53 dBc, which is 12 dB better than with conventional ZOH phase modulation. Furthermore, the system enables flexible upconversion to any frequency between 0.35 and 2.1 GHz from a fixed 1.5-GHz reference clock. The power consumption of a single engine is lower than 18 mW.
Machine learning in psychiatry: prediction and detection of mood disorders
(2021-04-16) Anttila, Lauri
Perustieteiden korkeakoulu | Bachelor's thesis
Multilevel Outphasing with Over-the-Air Combining in Large Antenna Arrays
(2023-12-01) Lampu, Vesa; Xu, Guixian; Brihuega, Alberto; Kosunen, Marko; Unnikrishnan, Vishnu; Ryynanen, Jussi; Fager, Christian; Valkama, Mikko; Anttila, Lauri
A1 Alkuperäisartikkeli tieteellisessä aikakauslehdessä
This article investigates the feasibility of combinerless multilevel outphasing transmitter as a potential architecture for large millimeter-wave (mmWave) phased arrays. We consider two distinct ways of distributing the component signals to the antennas and develop a model for the received signal at each radiated spatial direction from a phased array. Based on the received signal model, we derive expressions for the signal-to-distortion ratio as well as total power experienced at each spatial direction. Furthermore, antenna branch mismatches, overload distortion and quantization are considered, and an analytical model for the signal-to-distortion ratio at the intended receiver is derived. We additionally establish a model for comparing the achievable energy efficiency to those of the relevant reference methods. Extensive numerical experiments are carried out to verify the analytical works, and to assess the commonly used metrics of error vector magnitude (EVM) and total radiated power adjacent channel leakage ratio (TRP-ACLR). It is shown that the combinerless architecture is a valid option for mmWave phased arrays, demonstrating favorable EVM results and TRP-ACLR beyond the 28 dBc limit imposed by the 3GPP, even in the presence of the considered distortions. The conducted energy efficiency assessment shows that efficiency of the reference methods can be exceeded with sufficient amount of outphasing levels. The considered architecture is thus an interesting alternative for addressing the linearity vs. energy-efficiency challenge in mmWave phased-array systems.
Quantized Polar Transmitters for Power Efficient Massive MIMO Systems
(2021-04) Xu, Guixian; Lampu, Vesa; Kosunen, Marko; Stadius, Kari; Ryynanen, Jussi; Valkama, Mikko; Anttila, Lauri
A1 Alkuperäisartikkeli tieteellisessä aikakauslehdessä
This letter investigates the feasibility of the quantized digital polar transmitter architecture in a downlink multi-user massive multiple-input multiple-output orthogonal frequency-division multiplexing (MIMO-OFDM) system, where a low amplitude resolution and a moderate phase resolution are utilized. We derive a lower bound on the average sum-rate achievable with Gaussian signaling inputs and linear precoding by a simple diagonal approximation for the quantization distortion. The analysis and simulations demonstrate that the quantized polar transmitter can enable excellent performance in terms of average sum-rate throughput, symbol error rate (SER), and out-of-band (OOB) emission level, thus providing an attractive option for the traditional Cartesian architecture.
Reconfigurable Signal Processing and DSP Hardware Generator for 5G Transmitters
(2022-10-26) Ghosh, Agnimesh; Spelman, Andrei; Cheung, Tze Hin; Boopathy, Dhanashree; Unnikrishnan, Vishnu; Lampu, Vesa; Xu, Guixian; Anttila, Lauri; Stadius, Kari; Kosunen, Marko; Ryynänen, Jussi
A4 Artikkeli konferenssijulkaisussa
To impose the reconfigurability and reusability of digital circuits for millimeterwave transmitter architectures, high-speed digital signal processing architectures are explored. The digital front-end of these next-generation transmitters can be implemented up to the maximum operating frequency to meet the requirements of the 5G NR FR2 frequency bands. This paper presents an efficient implementation of a reconfigurable digital signal processor (DSP) that contains programmable multistage multirate filters, operable up to 4 GHz, and a flexible generator for polar, outphasing, and multilevel outphasing modulation. The system achieves an excellent ACLR of 42 dB and EVM degradation of 1.61% with a 7-bit phase signal at a sampling frequency of 4 GHz for outphasing modulation. Digital synthesis of the circuit in a 22 nm FDSOI process results in a core area of 0.12 mm2and an estimated power consumption of 142 mW for a 200 MHz bandwidth 5G NR baseband signal.
Spectral Effects of Discrete-Time Amplitude Levels in Digital-Intensive Wideband Radio Transmitters
(2018-05-04) Martelius, Mikko; Stadius, Kari; Lemberg, Jerry; Roverato, Enrico; Kosunen, Marko; Ryynänen, Jussi; Anttila, Lauri; Valkama, Mikko
A4 Artikkeli konferenssijulkaisussa
This paper examines one source of spectral degradation in polar and multilevel outphasing transmitters. The degradation is caused by the amplitude signal appearing at the transmitter output as a baseband component, in addition to the desired RF signal. This baseband component contains sampling images and quantization noise across the spectrum. Thus, it adds noise at the signal band where it cannot be filtered and limits the achievable ACLR, particularly in wideband LTE and 5G systems. We analyze the origin of this phenomenon and related effects of system and signal parameters, and propose three design solutions for eliminating or alleviating the problem. Our analysis and simulations demonstrate that using a voltage-subtracting power combiner cancels the described degradation, potentially leading to significant improvement in spectral performance.